CPU
The ARM® Cortex®-M4 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16- and 32-bit instructions to maximize code density and performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing including:
- Digital signal processing (DSP) instructions
- Single-cycle multiply and accumulate (MAC) instructions
- Hardware divide
- 8- and 16-bit single instruction multiple data (SIMD) instructions
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 Series. The section Electrical specification shows CPU performance parameters including wait states in different modes, CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark.
The ARM System Timer (SysTick) is present on the device. The SysTick's clock will only tick when the CPU is running or when the system is in debug interface mode.
Electrical specification
CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is executing the CoreMark® benchmark. It includes power regulator and clock base currents. All other blocks are IDLE.
| Symbol | Description | Min. | Typ. | Max. | Units | ||||
|---|---|---|---|---|---|---|---|---|---|
| WFLASH | CPU wait states, running from flash | 0 | 2 | ||||||
| WRAM | CPU wait states, running from RAM | 0 | |||||||
| CMFLASH | CoreMark1, running from flash | 144 | CoreMark | ||||||
| CMFLASH/MHz | CoreMark per MHz, running from flash | 2.25 | CoreMark/MHz | ||||||
| CMFLASH/mA | CoreMark per mA, running from flash, DCDC 3V | 65 | CoreMark/mA |
CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the device.
| Option / Module | Description | Implemented |
|---|---|---|
| Core options | ||
| NVIC | Nested vector interrupt controller | 30 vectors |
| PRIORITIES | Priority bits | 3 |
| WIC | Wakeup interrupt controller | NO |
| Endianness | Memory system endianness | Little endian |
| Bit-banding | Bit banded memory | NO |
| DWT | Data watchpoint and trace | NO |
| SysTick | System tick timer | YES |
| Modules | ||
| MPU | Memory protection unit | YES |
| FPU | Floating-point unit | NO |
| DAP | Debug access port | YES |
| ETM | Embedded trace macrocell | NO |
| ITM | Instrumentation trace macrocell | NO |
| TPIU | Trace port interface unit | NO |
| ETB | Embedded trace buffer | NO |
| FPB | Flash patch and breakpoint unit | YES |
| HTM | AMBA® AHB trace macrocell | NO |