BPROT — Block protection

The mechanism for protecting non-volatile memory can be used to prevent erroneous application code from erasing or writing to protected blocks.

Non-volatile memory can be protected from erases and writes depending on the settings in the CONFIG registers. One bit in a CONFIG register represents one protected block of 4 kB. There are multiple CONFIG registers to cover the whole range of the flash. Protected regions of program memory illustrates how the CONFIG bits map to the program memory space.

Important: If an erase or write to a protected block is detected, the CPU will hard fault. If an ERASEALL operation is attempted from the CPU while any block is protected, it will be blocked and the CPU will hard fault.

On reset, all the protection bits are cleared. To ensure safe operation, the first task after reset must be to set the protection bits. The only way of clearing protection bits is by resetting the device from any reset source.

The protection mechanism is turned off when in debug mode (when a debugger is connected) and the DISABLEINDEBUG register is set to disabled.

Figure 1. Protected regions of program memory

Registers

Table 1. Instances
Base address	Peripheral	Instance	Description	Configuration
0x40000000	BPROT	BPROT	Block protect

Table 2. Register overview
Register	Offset	Description
CONFIG0	0x600	Block protect configuration register 0
CONFIG1	0x604	Block protect configuration register 1
DISABLEINDEBUG	0x608	Disable protection mechanism in debug mode
UNUSED0	0x60C		Reserved

CONFIG0

Address offset: 0x600

Block protect configuration register 0

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A-f	RW	REGION[i] (i=0..31)										Enable protection for region i. Write '0' has no effect.
			Disabled	0								Protection disabled
			Enabled	1								Protection enabled

CONFIG1

Address offset: 0x604

Block protect configuration register 1

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A-P	RW	REGION[i+32] (i=0..15)										Enable protection for region i+32. Write '0' has no effect.
			Disabled	0								Protection disabled
			Enabled	1								Protection enabled

DISABLEINDEBUG

Address offset: 0x608

Disable protection mechanism in debug mode

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	Access	Field	Value ID	Value								Description
A	RW	DISABLEINDEBUG										Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode.
			Disabled	1								Disabled in debug
			Enabled	0								Enabled in debug