RTC — Real-time counter

The RTC will run off the LFCLK.

The COUNTER resolution will therefore be 30.517 μs. Depending on the source, the RTC is able to run while the HFCLK is OFF and PCLK16M is not available.

The software has to explicitely start LFCLK before using the RTC.

See CLOCK — Clock control for more information about clock sources.

Counter increment frequency:

    fRTC [kHz] = 32.768 / (PRESCALER + 1 )
    

The PRESCALER register is read/write when the RTC is stopped. The PRESCALER register is read-only once the RTC is STARTed. Writing to the PRESCALER register when the RTC is started has no effect.

The PRESCALER is restarted on START, CLEAR and TRIGOVRFLW, that is, the prescaler value is latched to an internal register (<<PRESC>>) on these tasks.

Examples:

1. Desired COUNTER frequency 100 Hz (10 ms counter period)

   PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327

   f_RTC = 99.9 Hz

   10009.576 μs counter period

2. Desired COUNTER frequency 8 Hz (125 ms counter period)

   PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095

   f_RTC = 8 Hz

   125 ms counter period

The COUNTER increments on LFCLK when the internal PRESCALER register (<<PRESC>>) is 0x00. <<PRESC>> is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment of the COUNTER. The TICK event is disabled by default.

Figure 2. Timing diagram - COUNTER_PRESCALER_0

Figure 3. Timing diagram - COUNTER_PRESCALER_1

The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition.

OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0.

The TICK event enables low power "tick-less" RTOS implementation as it optionally provides a regular interrupt source for a RTOS without the need to use the ARM® SysTick feature.

Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping RTOS scheduling active.

To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M and HFCLK being requested when those events are triggered. This is managed using the EVTEN register.

For example, if the TICK event is not required for an application, this event should be disabled as it is frequently occurring and may increase power consumption if HFCLK otherwise could be powered down for long durations.

This means that the RTC implements a slightly different task and event system compared to the standard system described in Peripheral interface. The RTC task and event system is illustrated in Tasks, events and interrupts in the RTC.

Figure 4. Tasks, events and interrupts in the RTC

There are a number of Compare registers.

For more information, see Registers.

When setting a compare register, the following behavior of the RTC compare event should be noted:

• If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event.
  Figure 5. Timing diagram - COMPARE_CLEAR
  

  

  
  
• If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a COMPARE event.
  Figure 6. Timing diagram - COMPARE_START
  

  

  
  
• COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N.
  Figure 7. Timing diagram - COMPARE
  

  

  
  
• If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2.
  Figure 8. Timing diagram - COMPARE_N+2
  

  

  
  
• If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
  Figure 9. Timing diagram - COMPARE_N+1
  

  

  
  

• If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a match may trigger on the previous CC value before the new value takes effect. If the current CC value greater than N+2 when the new value is written, there will be no event due to the old value.

  Figure 10. Timing diagram - COMPARE_N-1
  

  

  
  

Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not synchronous to the faster PCLK16M.

Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the register which is actually modified each time the RTC ticks. These registers must be synchronised between clock domains (PCLK16M and LFCLK).

The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow.

1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to clock a falling edge and rising of the LFCLK. This is between 15.2585 μs and 45.7755 μs – rounded to 15 μs and 46 μs for the remainder of the section.
   Figure 11. Timing diagram - DELAY_CLEAR
   

   

   
   
   Figure 12. Timing diagram - DELAY_STOP
   

   

   
   
2. The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the first increment of COUNTER (and instance of TICK event) will be typically after 30.5 μs +/-15 μs. In some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to ~250 μs. The software should therefore wait for the first TICK if it has to make sure the RTC is running. Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK, but the update will then be delayed by the same amount of time of up to ~250 us. The figures show the smallest and largest delays to on the START task which appears as a +/-15 μs jitter on the first COUNTER increment.
   Figure 13. Timing diagram - JITTER_START-
   

   

   
   
   Figure 14. Timing diagram - JITTER_START+
   

   

   
   

To read the COUNTER register, the internal <<COUNTER>> value is sampled.

To ensure that the <<COUNTER>> is safely sampled (considering an LFCLK transition may occur during a read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal. The Read takes the CPU 2 cycles in addition resulting in the COUNTER register read taking a fixed five PCLK16M clock cycles.

Figure 15. Timing diagram - COUNTER_READ