PPI — Programmable peripheral interconnect

The Programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI.

Figure 1. PPI block diagram

The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups in the same way as ordinary PPI channels.

Table 1. Configurable and fixed PPI channels
InstanceChannelNumber of channelsNumber of groups
PPI0-19206
PPI (fixed)20-3112

The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel is composed of three end point registers, one EEP and two TEPs. A peripheral task is connected to a TEP using the address of the task register associated with the task. Similarly, a peripheral event is connected to an EEP using the address of the event register associated with the event.

On each PPI channel, the signals are synchronized to the 16 MHz clock, to avoid any internal violation of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period.

Note that shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz synchronization, and are therefore not delayed.

Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].

There are two ways of enabling and disabling PPI channels:

  • Enable or disable PPI channels individually using the CHEN, CHENSET, and CHENCLR registers.
  • Enable or disable PPI channels in PPI channel groups through the groups’ ENABLE and DISABLE tasks. Prior to these tasks being triggered, the PPI channel group must be configured to define which PPI channels belongs to which groups.

Note that when a channel belongs to two groups m and n, and CHG[m].EN and CHG[n].DIS occur simultaneously (m and n can be equal or different), EN on that channel has priority.

PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means they can be hooked up to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple channels and one task can be triggered by multiple events in the same way.

Pre-programmed channels

Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for these channels are still programmable and can be used by the application.

For a list of pre-programmed PPI channels, see the table below.

Table 2. Pre-programmed channels
ChannelEEPTEP
20TIMER0->EVENTS_COMPARE[0]RADIO->TASKS_TXEN
21TIMER0->EVENTS_COMPARE[0]RADIO->TASKS_RXEN
22TIMER0->EVENTS_COMPARE[1]RADIO->TASKS_DISABLE
23RADIO->EVENTS_BCMATCHAAR->TASKS_START
24RADIO->EVENTS_READYCCM->TASKS_KSGEN
25RADIO->EVENTS_ADDRESSCCM->TASKS_CRYPT
26RADIO->EVENTS_ADDRESSTIMER0->TASKS_CAPTURE[1]
27RADIO->EVENTS_ENDTIMER0->TASKS_CAPTURE[2]
28RTC0->EVENTS_COMPARE[0]RADIO->TASKS_TXEN
29RTC0->EVENTS_COMPARE[0]RADIO->TASKS_RXEN
30RTC0->EVENTS_COMPARE[0]TIMER0->TASKS_CLEAR
31RTC0->EVENTS_COMPARE[0]TIMER0->TASKS_START

Registers

Table 3. Instances
Base addressPeripheralInstanceDescriptionConfiguration
0x4001F000PPIPPI

Programmable Peripheral Interconnect

  
Table 4. Register Overview
RegisterOffsetDescription
TASKS_CHG[0].EN0x000

Enable channel group 0

 
TASKS_CHG[0].DIS0x004

Disable channel group 0

 
TASKS_CHG[1].EN0x008

Enable channel group 1

 
TASKS_CHG[1].DIS0x00C

Disable channel group 1

 
TASKS_CHG[2].EN0x010

Enable channel group 2

 
TASKS_CHG[2].DIS0x014

Disable channel group 2

 
TASKS_CHG[3].EN0x018

Enable channel group 3

 
TASKS_CHG[3].DIS0x01C

Disable channel group 3

 
TASKS_CHG[4].EN0x020

Enable channel group 4

 
TASKS_CHG[4].DIS0x024

Disable channel group 4

 
TASKS_CHG[5].EN0x028

Enable channel group 5

 
TASKS_CHG[5].DIS0x02C

Disable channel group 5

 
CHEN0x500

Channel enable register

 
CHENSET0x504

Channel enable set register

 
CHENCLR0x508

Channel enable clear register

 
CH[0].EEP0x510

Channel 0 event end-point

 
CH[0].TEP0x514

Channel 0 task end-point

 
CH[1].EEP0x518

Channel 1 event end-point

 
CH[1].TEP0x51C

Channel 1 task end-point

 
CH[2].EEP0x520

Channel 2 event end-point

 
CH[2].TEP0x524

Channel 2 task end-point

 
CH[3].EEP0x528

Channel 3 event end-point

 
CH[3].TEP0x52C

Channel 3 task end-point

 
CH[4].EEP0x530

Channel 4 event end-point

 
CH[4].TEP0x534

Channel 4 task end-point

 
CH[5].EEP0x538

Channel 5 event end-point

 
CH[5].TEP0x53C

Channel 5 task end-point

 
CH[6].EEP0x540

Channel 6 event end-point

 
CH[6].TEP0x544

Channel 6 task end-point

 
CH[7].EEP0x548

Channel 7 event end-point

 
CH[7].TEP0x54C

Channel 7 task end-point

 
CH[8].EEP0x550

Channel 8 event end-point

 
CH[8].TEP0x554

Channel 8 task end-point

 
CH[9].EEP0x558

Channel 9 event end-point

 
CH[9].TEP0x55C

Channel 9 task end-point

 
CH[10].EEP0x560

Channel 10 event end-point

 
CH[10].TEP0x564

Channel 10 task end-point

 
CH[11].EEP0x568

Channel 11 event end-point

 
CH[11].TEP0x56C

Channel 11 task end-point

 
CH[12].EEP0x570

Channel 12 event end-point

 
CH[12].TEP0x574

Channel 12 task end-point

 
CH[13].EEP0x578

Channel 13 event end-point

 
CH[13].TEP0x57C

Channel 13 task end-point

 
CH[14].EEP0x580

Channel 14 event end-point

 
CH[14].TEP0x584

Channel 14 task end-point

 
CH[15].EEP0x588

Channel 15 event end-point

 
CH[15].TEP0x58C

Channel 15 task end-point

 
CH[16].EEP0x590

Channel 16 event end-point

 
CH[16].TEP0x594

Channel 16 task end-point

 
CH[17].EEP0x598

Channel 17 event end-point

 
CH[17].TEP0x59C

Channel 17 task end-point

 
CH[18].EEP0x5A0

Channel 18 event end-point

 
CH[18].TEP0x5A4

Channel 18 task end-point

 
CH[19].EEP0x5A8

Channel 19 event end-point

 
CH[19].TEP0x5AC

Channel 19 task end-point

 
CHG[0]0x800

Channel group 0

 
CHG[1]0x804

Channel group 1

 
CHG[2]0x808

Channel group 2

 
CHG[3]0x80C

Channel group 3

 
CHG[4]0x810

Channel group 4

 
CHG[5]0x814

Channel group 5

 
FORK[0].TEP0x910

Channel 0 task end-point

 
FORK[1].TEP0x914

Channel 1 task end-point

 
FORK[2].TEP0x918

Channel 2 task end-point

 
FORK[3].TEP0x91C

Channel 3 task end-point

 
FORK[4].TEP0x920

Channel 4 task end-point

 
FORK[5].TEP0x924

Channel 5 task end-point

 
FORK[6].TEP0x928

Channel 6 task end-point

 
FORK[7].TEP0x92C

Channel 7 task end-point

 
FORK[8].TEP0x930

Channel 8 task end-point

 
FORK[9].TEP0x934

Channel 9 task end-point

 
FORK[10].TEP0x938

Channel 10 task end-point

 
FORK[11].TEP0x93C

Channel 11 task end-point

 
FORK[12].TEP0x940

Channel 12 task end-point

 
FORK[13].TEP0x944

Channel 13 task end-point

 
FORK[14].TEP0x948

Channel 14 task end-point

 
FORK[15].TEP0x94C

Channel 15 task end-point

 
FORK[16].TEP0x950

Channel 16 task end-point

 
FORK[17].TEP0x954

Channel 17 task end-point

 
FORK[18].TEP0x958

Channel 18 task end-point

 
FORK[19].TEP0x95C

Channel 19 task end-point

 
FORK[20].TEP0x960

Channel 20 task end-point

 
FORK[21].TEP0x964

Channel 21 task end-point

 
FORK[22].TEP0x968

Channel 22 task end-point

 
FORK[23].TEP0x96C

Channel 23 task end-point

 
FORK[24].TEP0x970

Channel 24 task end-point

 
FORK[25].TEP0x974

Channel 25 task end-point

 
FORK[26].TEP0x978

Channel 26 task end-point

 
FORK[27].TEP0x97C

Channel 27 task end-point

 
FORK[28].TEP0x980

Channel 28 task end-point

 
FORK[29].TEP0x984

Channel 29 task end-point

 
FORK[30].TEP0x988

Channel 30 task end-point

 
FORK[31].TEP0x98C

Channel 31 task end-point

 

CHEN

Address offset: 0x500

Channel enable register

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Enable or disable channel 0

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

BRW

CH1

  

Enable or disable channel 1

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

CRW

CH2

  

Enable or disable channel 2

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

DRW

CH3

  

Enable or disable channel 3

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

ERW

CH4

  

Enable or disable channel 4

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

FRW

CH5

  

Enable or disable channel 5

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

GRW

CH6

  

Enable or disable channel 6

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

HRW

CH7

  

Enable or disable channel 7

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

IRW

CH8

  

Enable or disable channel 8

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

JRW

CH9

  

Enable or disable channel 9

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

KRW

CH10

  

Enable or disable channel 10

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

LRW

CH11

  

Enable or disable channel 11

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

MRW

CH12

  

Enable or disable channel 12

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

NRW

CH13

  

Enable or disable channel 13

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

ORW

CH14

  

Enable or disable channel 14

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

PRW

CH15

  

Enable or disable channel 15

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

QRW

CH16

  

Enable or disable channel 16

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

RRW

CH17

  

Enable or disable channel 17

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

SRW

CH18

  

Enable or disable channel 18

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

TRW

CH19

  

Enable or disable channel 19

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

URW

CH20

  

Enable or disable channel 20

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

VRW

CH21

  

Enable or disable channel 21

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

WRW

CH22

  

Enable or disable channel 22

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

XRW

CH23

  

Enable or disable channel 23

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

YRW

CH24

  

Enable or disable channel 24

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

ZRW

CH25

  

Enable or disable channel 25

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

aRW

CH26

  

Enable or disable channel 26

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

bRW

CH27

  

Enable or disable channel 27

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

cRW

CH28

  

Enable or disable channel 28

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

dRW

CH29

  

Enable or disable channel 29

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

eRW

CH30

  

Enable or disable channel 30

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

fRW

CH31

  

Enable or disable channel 31

   

Disabled

0

Disable channel

   

Enabled

1

Enable channel

 

CHENSET

Address offset: 0x504

Channel enable set register

Read: reads value of CH{i} field in CHEN register.

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Channel 0 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

BRW

CH1

  

Channel 1 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

CRW

CH2

  

Channel 2 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

DRW

CH3

  

Channel 3 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

ERW

CH4

  

Channel 4 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

FRW

CH5

  

Channel 5 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

GRW

CH6

  

Channel 6 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

HRW

CH7

  

Channel 7 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

IRW

CH8

  

Channel 8 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

JRW

CH9

  

Channel 9 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

KRW

CH10

  

Channel 10 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

LRW

CH11

  

Channel 11 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

MRW

CH12

  

Channel 12 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

NRW

CH13

  

Channel 13 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

ORW

CH14

  

Channel 14 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

PRW

CH15

  

Channel 15 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

QRW

CH16

  

Channel 16 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

RRW

CH17

  

Channel 17 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

SRW

CH18

  

Channel 18 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

TRW

CH19

  

Channel 19 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

URW

CH20

  

Channel 20 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

VRW

CH21

  

Channel 21 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

WRW

CH22

  

Channel 22 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

XRW

CH23

  

Channel 23 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

YRW

CH24

  

Channel 24 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

ZRW

CH25

  

Channel 25 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

aRW

CH26

  

Channel 26 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

bRW

CH27

  

Channel 27 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

cRW

CH28

  

Channel 28 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

dRW

CH29

  

Channel 29 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

eRW

CH30

  

Channel 30 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

fRW

CH31

  

Channel 31 enable set register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Set

1

Write: Enable channel

 

CHENCLR

Address offset: 0x508

Channel enable clear register

Read: reads value of CH{i} field in CHEN register.

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Channel 0 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

BRW

CH1

  

Channel 1 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

CRW

CH2

  

Channel 2 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

DRW

CH3

  

Channel 3 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

ERW

CH4

  

Channel 4 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

FRW

CH5

  

Channel 5 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

GRW

CH6

  

Channel 6 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

HRW

CH7

  

Channel 7 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

IRW

CH8

  

Channel 8 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

JRW

CH9

  

Channel 9 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

KRW

CH10

  

Channel 10 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

LRW

CH11

  

Channel 11 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

MRW

CH12

  

Channel 12 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

NRW

CH13

  

Channel 13 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

ORW

CH14

  

Channel 14 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

PRW

CH15

  

Channel 15 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

QRW

CH16

  

Channel 16 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

RRW

CH17

  

Channel 17 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

SRW

CH18

  

Channel 18 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

TRW

CH19

  

Channel 19 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

URW

CH20

  

Channel 20 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

VRW

CH21

  

Channel 21 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

WRW

CH22

  

Channel 22 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

XRW

CH23

  

Channel 23 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

YRW

CH24

  

Channel 24 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

ZRW

CH25

  

Channel 25 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

aRW

CH26

  

Channel 26 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

bRW

CH27

  

Channel 27 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

cRW

CH28

  

Channel 28 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

dRW

CH29

  

Channel 29 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

eRW

CH30

  

Channel 30 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

fRW

CH31

  

Channel 31 enable clear register. Writing '0' has no effect

   

Disabled

0

Read: channel disabled

   

Enabled

1

Read: channel enabled

   

Clear

1

Write: disable channel

 

CH[0].EEP

Address offset: 0x510

Channel 0 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[0].TEP

Address offset: 0x514

Channel 0 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[1].EEP

Address offset: 0x518

Channel 1 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[1].TEP

Address offset: 0x51C

Channel 1 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[2].EEP

Address offset: 0x520

Channel 2 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[2].TEP

Address offset: 0x524

Channel 2 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[3].EEP

Address offset: 0x528

Channel 3 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[3].TEP

Address offset: 0x52C

Channel 3 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[4].EEP

Address offset: 0x530

Channel 4 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[4].TEP

Address offset: 0x534

Channel 4 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[5].EEP

Address offset: 0x538

Channel 5 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[5].TEP

Address offset: 0x53C

Channel 5 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[6].EEP

Address offset: 0x540

Channel 6 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[6].TEP

Address offset: 0x544

Channel 6 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[7].EEP

Address offset: 0x548

Channel 7 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[7].TEP

Address offset: 0x54C

Channel 7 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[8].EEP

Address offset: 0x550

Channel 8 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[8].TEP

Address offset: 0x554

Channel 8 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[9].EEP

Address offset: 0x558

Channel 9 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[9].TEP

Address offset: 0x55C

Channel 9 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[10].EEP

Address offset: 0x560

Channel 10 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[10].TEP

Address offset: 0x564

Channel 10 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[11].EEP

Address offset: 0x568

Channel 11 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[11].TEP

Address offset: 0x56C

Channel 11 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[12].EEP

Address offset: 0x570

Channel 12 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[12].TEP

Address offset: 0x574

Channel 12 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[13].EEP

Address offset: 0x578

Channel 13 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[13].TEP

Address offset: 0x57C

Channel 13 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[14].EEP

Address offset: 0x580

Channel 14 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[14].TEP

Address offset: 0x584

Channel 14 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[15].EEP

Address offset: 0x588

Channel 15 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[15].TEP

Address offset: 0x58C

Channel 15 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[16].EEP

Address offset: 0x590

Channel 16 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[16].TEP

Address offset: 0x594

Channel 16 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[17].EEP

Address offset: 0x598

Channel 17 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[17].TEP

Address offset: 0x59C

Channel 17 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[18].EEP

Address offset: 0x5A0

Channel 18 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[18].TEP

Address offset: 0x5A4

Channel 18 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CH[19].EEP

Address offset: 0x5A8

Channel 19 event end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

EEP

  

Pointer to event register. Accepts only addresses to registers from the Event group.

 

CH[19].TEP

Address offset: 0x5AC

Channel 19 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register. Accepts only addresses to registers from the Task group.

 

CHG[0]

Address offset: 0x800

Channel group 0

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Include or exclude channel 0

   

Excluded

0

Exclude

   

Included

1

Include

BRW

CH1

  

Include or exclude channel 1

   

Excluded

0

Exclude

   

Included

1

Include

CRW

CH2

  

Include or exclude channel 2

   

Excluded

0

Exclude

   

Included

1

Include

DRW

CH3

  

Include or exclude channel 3

   

Excluded

0

Exclude

   

Included

1

Include

ERW

CH4

  

Include or exclude channel 4

   

Excluded

0

Exclude

   

Included

1

Include

FRW

CH5

  

Include or exclude channel 5

   

Excluded

0

Exclude

   

Included

1

Include

GRW

CH6

  

Include or exclude channel 6

   

Excluded

0

Exclude

   

Included

1

Include

HRW

CH7

  

Include or exclude channel 7

   

Excluded

0

Exclude

   

Included

1

Include

IRW

CH8

  

Include or exclude channel 8

   

Excluded

0

Exclude

   

Included

1

Include

JRW

CH9

  

Include or exclude channel 9

   

Excluded

0

Exclude

   

Included

1

Include

KRW

CH10

  

Include or exclude channel 10

   

Excluded

0

Exclude

   

Included

1

Include

LRW

CH11

  

Include or exclude channel 11

   

Excluded

0

Exclude

   

Included

1

Include

MRW

CH12

  

Include or exclude channel 12

   

Excluded

0

Exclude

   

Included

1

Include

NRW

CH13

  

Include or exclude channel 13

   

Excluded

0

Exclude

   

Included

1

Include

ORW

CH14

  

Include or exclude channel 14

   

Excluded

0

Exclude

   

Included

1

Include

PRW

CH15

  

Include or exclude channel 15

   

Excluded

0

Exclude

   

Included

1

Include

QRW

CH16

  

Include or exclude channel 16

   

Excluded

0

Exclude

   

Included

1

Include

RRW

CH17

  

Include or exclude channel 17

   

Excluded

0

Exclude

   

Included

1

Include

SRW

CH18

  

Include or exclude channel 18

   

Excluded

0

Exclude

   

Included

1

Include

TRW

CH19

  

Include or exclude channel 19

   

Excluded

0

Exclude

   

Included

1

Include

URW

CH20

  

Include or exclude channel 20

   

Excluded

0

Exclude

   

Included

1

Include

VRW

CH21

  

Include or exclude channel 21

   

Excluded

0

Exclude

   

Included

1

Include

WRW

CH22

  

Include or exclude channel 22

   

Excluded

0

Exclude

   

Included

1

Include

XRW

CH23

  

Include or exclude channel 23

   

Excluded

0

Exclude

   

Included

1

Include

YRW

CH24

  

Include or exclude channel 24

   

Excluded

0

Exclude

   

Included

1

Include

ZRW

CH25

  

Include or exclude channel 25

   

Excluded

0

Exclude

   

Included

1

Include

aRW

CH26

  

Include or exclude channel 26

   

Excluded

0

Exclude

   

Included

1

Include

bRW

CH27

  

Include or exclude channel 27

   

Excluded

0

Exclude

   

Included

1

Include

cRW

CH28

  

Include or exclude channel 28

   

Excluded

0

Exclude

   

Included

1

Include

dRW

CH29

  

Include or exclude channel 29

   

Excluded

0

Exclude

   

Included

1

Include

eRW

CH30

  

Include or exclude channel 30

   

Excluded

0

Exclude

   

Included

1

Include

fRW

CH31

  

Include or exclude channel 31

   

Excluded

0

Exclude

   

Included

1

Include

 

CHG[1]

Address offset: 0x804

Channel group 1

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Include or exclude channel 0

   

Excluded

0

Exclude

   

Included

1

Include

BRW

CH1

  

Include or exclude channel 1

   

Excluded

0

Exclude

   

Included

1

Include

CRW

CH2

  

Include or exclude channel 2

   

Excluded

0

Exclude

   

Included

1

Include

DRW

CH3

  

Include or exclude channel 3

   

Excluded

0

Exclude

   

Included

1

Include

ERW

CH4

  

Include or exclude channel 4

   

Excluded

0

Exclude

   

Included

1

Include

FRW

CH5

  

Include or exclude channel 5

   

Excluded

0

Exclude

   

Included

1

Include

GRW

CH6

  

Include or exclude channel 6

   

Excluded

0

Exclude

   

Included

1

Include

HRW

CH7

  

Include or exclude channel 7

   

Excluded

0

Exclude

   

Included

1

Include

IRW

CH8

  

Include or exclude channel 8

   

Excluded

0

Exclude

   

Included

1

Include

JRW

CH9

  

Include or exclude channel 9

   

Excluded

0

Exclude

   

Included

1

Include

KRW

CH10

  

Include or exclude channel 10

   

Excluded

0

Exclude

   

Included

1

Include

LRW

CH11

  

Include or exclude channel 11

   

Excluded

0

Exclude

   

Included

1

Include

MRW

CH12

  

Include or exclude channel 12

   

Excluded

0

Exclude

   

Included

1

Include

NRW

CH13

  

Include or exclude channel 13

   

Excluded

0

Exclude

   

Included

1

Include

ORW

CH14

  

Include or exclude channel 14

   

Excluded

0

Exclude

   

Included

1

Include

PRW

CH15

  

Include or exclude channel 15

   

Excluded

0

Exclude

   

Included

1

Include

QRW

CH16

  

Include or exclude channel 16

   

Excluded

0

Exclude

   

Included

1

Include

RRW

CH17

  

Include or exclude channel 17

   

Excluded

0

Exclude

   

Included

1

Include

SRW

CH18

  

Include or exclude channel 18

   

Excluded

0

Exclude

   

Included

1

Include

TRW

CH19

  

Include or exclude channel 19

   

Excluded

0

Exclude

   

Included

1

Include

URW

CH20

  

Include or exclude channel 20

   

Excluded

0

Exclude

   

Included

1

Include

VRW

CH21

  

Include or exclude channel 21

   

Excluded

0

Exclude

   

Included

1

Include

WRW

CH22

  

Include or exclude channel 22

   

Excluded

0

Exclude

   

Included

1

Include

XRW

CH23

  

Include or exclude channel 23

   

Excluded

0

Exclude

   

Included

1

Include

YRW

CH24

  

Include or exclude channel 24

   

Excluded

0

Exclude

   

Included

1

Include

ZRW

CH25

  

Include or exclude channel 25

   

Excluded

0

Exclude

   

Included

1

Include

aRW

CH26

  

Include or exclude channel 26

   

Excluded

0

Exclude

   

Included

1

Include

bRW

CH27

  

Include or exclude channel 27

   

Excluded

0

Exclude

   

Included

1

Include

cRW

CH28

  

Include or exclude channel 28

   

Excluded

0

Exclude

   

Included

1

Include

dRW

CH29

  

Include or exclude channel 29

   

Excluded

0

Exclude

   

Included

1

Include

eRW

CH30

  

Include or exclude channel 30

   

Excluded

0

Exclude

   

Included

1

Include

fRW

CH31

  

Include or exclude channel 31

   

Excluded

0

Exclude

   

Included

1

Include

 

CHG[2]

Address offset: 0x808

Channel group 2

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Include or exclude channel 0

   

Excluded

0

Exclude

   

Included

1

Include

BRW

CH1

  

Include or exclude channel 1

   

Excluded

0

Exclude

   

Included

1

Include

CRW

CH2

  

Include or exclude channel 2

   

Excluded

0

Exclude

   

Included

1

Include

DRW

CH3

  

Include or exclude channel 3

   

Excluded

0

Exclude

   

Included

1

Include

ERW

CH4

  

Include or exclude channel 4

   

Excluded

0

Exclude

   

Included

1

Include

FRW

CH5

  

Include or exclude channel 5

   

Excluded

0

Exclude

   

Included

1

Include

GRW

CH6

  

Include or exclude channel 6

   

Excluded

0

Exclude

   

Included

1

Include

HRW

CH7

  

Include or exclude channel 7

   

Excluded

0

Exclude

   

Included

1

Include

IRW

CH8

  

Include or exclude channel 8

   

Excluded

0

Exclude

   

Included

1

Include

JRW

CH9

  

Include or exclude channel 9

   

Excluded

0

Exclude

   

Included

1

Include

KRW

CH10

  

Include or exclude channel 10

   

Excluded

0

Exclude

   

Included

1

Include

LRW

CH11

  

Include or exclude channel 11

   

Excluded

0

Exclude

   

Included

1

Include

MRW

CH12

  

Include or exclude channel 12

   

Excluded

0

Exclude

   

Included

1

Include

NRW

CH13

  

Include or exclude channel 13

   

Excluded

0

Exclude

   

Included

1

Include

ORW

CH14

  

Include or exclude channel 14

   

Excluded

0

Exclude

   

Included

1

Include

PRW

CH15

  

Include or exclude channel 15

   

Excluded

0

Exclude

   

Included

1

Include

QRW

CH16

  

Include or exclude channel 16

   

Excluded

0

Exclude

   

Included

1

Include

RRW

CH17

  

Include or exclude channel 17

   

Excluded

0

Exclude

   

Included

1

Include

SRW

CH18

  

Include or exclude channel 18

   

Excluded

0

Exclude

   

Included

1

Include

TRW

CH19

  

Include or exclude channel 19

   

Excluded

0

Exclude

   

Included

1

Include

URW

CH20

  

Include or exclude channel 20

   

Excluded

0

Exclude

   

Included

1

Include

VRW

CH21

  

Include or exclude channel 21

   

Excluded

0

Exclude

   

Included

1

Include

WRW

CH22

  

Include or exclude channel 22

   

Excluded

0

Exclude

   

Included

1

Include

XRW

CH23

  

Include or exclude channel 23

   

Excluded

0

Exclude

   

Included

1

Include

YRW

CH24

  

Include or exclude channel 24

   

Excluded

0

Exclude

   

Included

1

Include

ZRW

CH25

  

Include or exclude channel 25

   

Excluded

0

Exclude

   

Included

1

Include

aRW

CH26

  

Include or exclude channel 26

   

Excluded

0

Exclude

   

Included

1

Include

bRW

CH27

  

Include or exclude channel 27

   

Excluded

0

Exclude

   

Included

1

Include

cRW

CH28

  

Include or exclude channel 28

   

Excluded

0

Exclude

   

Included

1

Include

dRW

CH29

  

Include or exclude channel 29

   

Excluded

0

Exclude

   

Included

1

Include

eRW

CH30

  

Include or exclude channel 30

   

Excluded

0

Exclude

   

Included

1

Include

fRW

CH31

  

Include or exclude channel 31

   

Excluded

0

Exclude

   

Included

1

Include

 

CHG[3]

Address offset: 0x80C

Channel group 3

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Include or exclude channel 0

   

Excluded

0

Exclude

   

Included

1

Include

BRW

CH1

  

Include or exclude channel 1

   

Excluded

0

Exclude

   

Included

1

Include

CRW

CH2

  

Include or exclude channel 2

   

Excluded

0

Exclude

   

Included

1

Include

DRW

CH3

  

Include or exclude channel 3

   

Excluded

0

Exclude

   

Included

1

Include

ERW

CH4

  

Include or exclude channel 4

   

Excluded

0

Exclude

   

Included

1

Include

FRW

CH5

  

Include or exclude channel 5

   

Excluded

0

Exclude

   

Included

1

Include

GRW

CH6

  

Include or exclude channel 6

   

Excluded

0

Exclude

   

Included

1

Include

HRW

CH7

  

Include or exclude channel 7

   

Excluded

0

Exclude

   

Included

1

Include

IRW

CH8

  

Include or exclude channel 8

   

Excluded

0

Exclude

   

Included

1

Include

JRW

CH9

  

Include or exclude channel 9

   

Excluded

0

Exclude

   

Included

1

Include

KRW

CH10

  

Include or exclude channel 10

   

Excluded

0

Exclude

   

Included

1

Include

LRW

CH11

  

Include or exclude channel 11

   

Excluded

0

Exclude

   

Included

1

Include

MRW

CH12

  

Include or exclude channel 12

   

Excluded

0

Exclude

   

Included

1

Include

NRW

CH13

  

Include or exclude channel 13

   

Excluded

0

Exclude

   

Included

1

Include

ORW

CH14

  

Include or exclude channel 14

   

Excluded

0

Exclude

   

Included

1

Include

PRW

CH15

  

Include or exclude channel 15

   

Excluded

0

Exclude

   

Included

1

Include

QRW

CH16

  

Include or exclude channel 16

   

Excluded

0

Exclude

   

Included

1

Include

RRW

CH17

  

Include or exclude channel 17

   

Excluded

0

Exclude

   

Included

1

Include

SRW

CH18

  

Include or exclude channel 18

   

Excluded

0

Exclude

   

Included

1

Include

TRW

CH19

  

Include or exclude channel 19

   

Excluded

0

Exclude

   

Included

1

Include

URW

CH20

  

Include or exclude channel 20

   

Excluded

0

Exclude

   

Included

1

Include

VRW

CH21

  

Include or exclude channel 21

   

Excluded

0

Exclude

   

Included

1

Include

WRW

CH22

  

Include or exclude channel 22

   

Excluded

0

Exclude

   

Included

1

Include

XRW

CH23

  

Include or exclude channel 23

   

Excluded

0

Exclude

   

Included

1

Include

YRW

CH24

  

Include or exclude channel 24

   

Excluded

0

Exclude

   

Included

1

Include

ZRW

CH25

  

Include or exclude channel 25

   

Excluded

0

Exclude

   

Included

1

Include

aRW

CH26

  

Include or exclude channel 26

   

Excluded

0

Exclude

   

Included

1

Include

bRW

CH27

  

Include or exclude channel 27

   

Excluded

0

Exclude

   

Included

1

Include

cRW

CH28

  

Include or exclude channel 28

   

Excluded

0

Exclude

   

Included

1

Include

dRW

CH29

  

Include or exclude channel 29

   

Excluded

0

Exclude

   

Included

1

Include

eRW

CH30

  

Include or exclude channel 30

   

Excluded

0

Exclude

   

Included

1

Include

fRW

CH31

  

Include or exclude channel 31

   

Excluded

0

Exclude

   

Included

1

Include

 

CHG[4]

Address offset: 0x810

Channel group 4

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Include or exclude channel 0

   

Excluded

0

Exclude

   

Included

1

Include

BRW

CH1

  

Include or exclude channel 1

   

Excluded

0

Exclude

   

Included

1

Include

CRW

CH2

  

Include or exclude channel 2

   

Excluded

0

Exclude

   

Included

1

Include

DRW

CH3

  

Include or exclude channel 3

   

Excluded

0

Exclude

   

Included

1

Include

ERW

CH4

  

Include or exclude channel 4

   

Excluded

0

Exclude

   

Included

1

Include

FRW

CH5

  

Include or exclude channel 5

   

Excluded

0

Exclude

   

Included

1

Include

GRW

CH6

  

Include or exclude channel 6

   

Excluded

0

Exclude

   

Included

1

Include

HRW

CH7

  

Include or exclude channel 7

   

Excluded

0

Exclude

   

Included

1

Include

IRW

CH8

  

Include or exclude channel 8

   

Excluded

0

Exclude

   

Included

1

Include

JRW

CH9

  

Include or exclude channel 9

   

Excluded

0

Exclude

   

Included

1

Include

KRW

CH10

  

Include or exclude channel 10

   

Excluded

0

Exclude

   

Included

1

Include

LRW

CH11

  

Include or exclude channel 11

   

Excluded

0

Exclude

   

Included

1

Include

MRW

CH12

  

Include or exclude channel 12

   

Excluded

0

Exclude

   

Included

1

Include

NRW

CH13

  

Include or exclude channel 13

   

Excluded

0

Exclude

   

Included

1

Include

ORW

CH14

  

Include or exclude channel 14

   

Excluded

0

Exclude

   

Included

1

Include

PRW

CH15

  

Include or exclude channel 15

   

Excluded

0

Exclude

   

Included

1

Include

QRW

CH16

  

Include or exclude channel 16

   

Excluded

0

Exclude

   

Included

1

Include

RRW

CH17

  

Include or exclude channel 17

   

Excluded

0

Exclude

   

Included

1

Include

SRW

CH18

  

Include or exclude channel 18

   

Excluded

0

Exclude

   

Included

1

Include

TRW

CH19

  

Include or exclude channel 19

   

Excluded

0

Exclude

   

Included

1

Include

URW

CH20

  

Include or exclude channel 20

   

Excluded

0

Exclude

   

Included

1

Include

VRW

CH21

  

Include or exclude channel 21

   

Excluded

0

Exclude

   

Included

1

Include

WRW

CH22

  

Include or exclude channel 22

   

Excluded

0

Exclude

   

Included

1

Include

XRW

CH23

  

Include or exclude channel 23

   

Excluded

0

Exclude

   

Included

1

Include

YRW

CH24

  

Include or exclude channel 24

   

Excluded

0

Exclude

   

Included

1

Include

ZRW

CH25

  

Include or exclude channel 25

   

Excluded

0

Exclude

   

Included

1

Include

aRW

CH26

  

Include or exclude channel 26

   

Excluded

0

Exclude

   

Included

1

Include

bRW

CH27

  

Include or exclude channel 27

   

Excluded

0

Exclude

   

Included

1

Include

cRW

CH28

  

Include or exclude channel 28

   

Excluded

0

Exclude

   

Included

1

Include

dRW

CH29

  

Include or exclude channel 29

   

Excluded

0

Exclude

   

Included

1

Include

eRW

CH30

  

Include or exclude channel 30

   

Excluded

0

Exclude

   

Included

1

Include

fRW

CH31

  

Include or exclude channel 31

   

Excluded

0

Exclude

   

Included

1

Include

 

CHG[5]

Address offset: 0x814

Channel group 5

Bit number313029282726252423222120191817161514131211109876543210
IdfedcbaZYXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

CH0

  

Include or exclude channel 0

   

Excluded

0

Exclude

   

Included

1

Include

BRW

CH1

  

Include or exclude channel 1

   

Excluded

0

Exclude

   

Included

1

Include

CRW

CH2

  

Include or exclude channel 2

   

Excluded

0

Exclude

   

Included

1

Include

DRW

CH3

  

Include or exclude channel 3

   

Excluded

0

Exclude

   

Included

1

Include

ERW

CH4

  

Include or exclude channel 4

   

Excluded

0

Exclude

   

Included

1

Include

FRW

CH5

  

Include or exclude channel 5

   

Excluded

0

Exclude

   

Included

1

Include

GRW

CH6

  

Include or exclude channel 6

   

Excluded

0

Exclude

   

Included

1

Include

HRW

CH7

  

Include or exclude channel 7

   

Excluded

0

Exclude

   

Included

1

Include

IRW

CH8

  

Include or exclude channel 8

   

Excluded

0

Exclude

   

Included

1

Include

JRW

CH9

  

Include or exclude channel 9

   

Excluded

0

Exclude

   

Included

1

Include

KRW

CH10

  

Include or exclude channel 10

   

Excluded

0

Exclude

   

Included

1

Include

LRW

CH11

  

Include or exclude channel 11

   

Excluded

0

Exclude

   

Included

1

Include

MRW

CH12

  

Include or exclude channel 12

   

Excluded

0

Exclude

   

Included

1

Include

NRW

CH13

  

Include or exclude channel 13

   

Excluded

0

Exclude

   

Included

1

Include

ORW

CH14

  

Include or exclude channel 14

   

Excluded

0

Exclude

   

Included

1

Include

PRW

CH15

  

Include or exclude channel 15

   

Excluded

0

Exclude

   

Included

1

Include

QRW

CH16

  

Include or exclude channel 16

   

Excluded

0

Exclude

   

Included

1

Include

RRW

CH17

  

Include or exclude channel 17

   

Excluded

0

Exclude

   

Included

1

Include

SRW

CH18

  

Include or exclude channel 18

   

Excluded

0

Exclude

   

Included

1

Include

TRW

CH19

  

Include or exclude channel 19

   

Excluded

0

Exclude

   

Included

1

Include

URW

CH20

  

Include or exclude channel 20

   

Excluded

0

Exclude

   

Included

1

Include

VRW

CH21

  

Include or exclude channel 21

   

Excluded

0

Exclude

   

Included

1

Include

WRW

CH22

  

Include or exclude channel 22

   

Excluded

0

Exclude

   

Included

1

Include

XRW

CH23

  

Include or exclude channel 23

   

Excluded

0

Exclude

   

Included

1

Include

YRW

CH24

  

Include or exclude channel 24

   

Excluded

0

Exclude

   

Included

1

Include

ZRW

CH25

  

Include or exclude channel 25

   

Excluded

0

Exclude

   

Included

1

Include

aRW

CH26

  

Include or exclude channel 26

   

Excluded

0

Exclude

   

Included

1

Include

bRW

CH27

  

Include or exclude channel 27

   

Excluded

0

Exclude

   

Included

1

Include

cRW

CH28

  

Include or exclude channel 28

   

Excluded

0

Exclude

   

Included

1

Include

dRW

CH29

  

Include or exclude channel 29

   

Excluded

0

Exclude

   

Included

1

Include

eRW

CH30

  

Include or exclude channel 30

   

Excluded

0

Exclude

   

Included

1

Include

fRW

CH31

  

Include or exclude channel 31

   

Excluded

0

Exclude

   

Included

1

Include

 

FORK[0].TEP

Address offset: 0x910

Channel 0 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[1].TEP

Address offset: 0x914

Channel 1 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[2].TEP

Address offset: 0x918

Channel 2 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[3].TEP

Address offset: 0x91C

Channel 3 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[4].TEP

Address offset: 0x920

Channel 4 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[5].TEP

Address offset: 0x924

Channel 5 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[6].TEP

Address offset: 0x928

Channel 6 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[7].TEP

Address offset: 0x92C

Channel 7 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[8].TEP

Address offset: 0x930

Channel 8 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[9].TEP

Address offset: 0x934

Channel 9 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[10].TEP

Address offset: 0x938

Channel 10 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[11].TEP

Address offset: 0x93C

Channel 11 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[12].TEP

Address offset: 0x940

Channel 12 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[13].TEP

Address offset: 0x944

Channel 13 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[14].TEP

Address offset: 0x948

Channel 14 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[15].TEP

Address offset: 0x94C

Channel 15 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[16].TEP

Address offset: 0x950

Channel 16 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[17].TEP

Address offset: 0x954

Channel 17 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[18].TEP

Address offset: 0x958

Channel 18 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[19].TEP

Address offset: 0x95C

Channel 19 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[20].TEP

Address offset: 0x960

Channel 20 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[21].TEP

Address offset: 0x964

Channel 21 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[22].TEP

Address offset: 0x968

Channel 22 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[23].TEP

Address offset: 0x96C

Channel 23 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[24].TEP

Address offset: 0x970

Channel 24 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[25].TEP

Address offset: 0x974

Channel 25 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[26].TEP

Address offset: 0x978

Channel 26 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[27].TEP

Address offset: 0x97C

Channel 27 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[28].TEP

Address offset: 0x980

Channel 28 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[29].TEP

Address offset: 0x984

Channel 29 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[30].TEP

Address offset: 0x988

Channel 30 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register

 

FORK[31].TEP

Address offset: 0x98C

Channel 31 task end-point

Bit number313029282726252423222120191817161514131211109876543210
IdAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IdRWFieldValue IdValueDescription
ARW

TEP

  

Pointer to task register