Pin assignments

The pin assignment figures and tables describe the pinouts for the product variants of the chip.

The nRF52833 device provides flexibility regarding GPIO pin routing and configuration. However, some pins have limitations or recommendations for pin configurations and uses.

aQFN73 ball assignments

The ball assignment figure and table in the following section describe the assignments for this variant of the chip.

Figure 1. aQFN73™ ball assignments, top view

aQFN73 ball assignments

Table 1. aQFN73 ball assignments
PinNameFunctionDescriptionRecommended usage
A8

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O

Analog input

Standard drive, low frequency I/O only
A10

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O

Analog input

Standard drive, low frequency I/O only
A12

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O

Analog input

Standard drive, low frequency I/O only
A14P0.19Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
A16P1.05Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
A18N.C.
A20P0.25Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
A22VDDPowerPower supply
A23XC2Analog inputConnection for 32 MHz crystal
B1VDDPowerPower supply
B3DCCPowerDC/DC converter output
B5DEC4Power1.3 V regulator supply decouplingMust be connected to DEC6 (pin E24)
B7VSSPowerGround
B9

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O

Analog input

Standard drive, low frequency I/O only
B11

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O

Analog input

Standard drive, low frequency I/O only
B13

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O

Analog input

Standard drive, low frequency I/O only
B15P1.03Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
B17P0.23Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
B19N.C.
B24XC1Analog inputConnection for 32 MHz crystal
C1DEC1Power1.1 V regulator supply decoupling
D2

P0.00

XL1

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

D23DEC3PowerPower supply, decoupling
E24DEC6Power1.3 V regulator supply decouplingMust be connected to DEC4 (pin B5)
F2

P0.01

XL2

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

F23VSS_PAPowerGround (radio supply)
G1P0.26Digital I/OGeneral purpose I/O
H2P0.27Digital I/OGeneral purpose I/O
H23ANTRFSingle-ended radio antenna connectionSee Reference circuitry for guidelines on how to ensure good RF performance
J1

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O

Analog input

J24

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

Standard drive, low frequency I/O only
K2

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O

Analog input

L1P0.06Digital I/OGeneral purpose I/O
L24

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

Standard drive, low frequency I/O only
M2

P0.07

TRACECLK

Digital I/O

Trace clock

General purpose I/O

Trace buffer clock

N1P0.08Digital I/OGeneral purpose I/O
N24

DEC5

Not connected

Power

1.3 V regulator supply decoupling for build codes Axx and earlier.

Not connected for build codes Bxx and later.

P2P1.08Digital I/OGeneral purpose I/O
P23P1.07Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
R1

P1.09

TRACEDATA3

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[3]

R24P1.06Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
T2

P0.11

TRACEDATA2

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[2]

T23N.C.
U1

P0.12

TRACEDATA1

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[1]

U24P1.04Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
V23N.C.
W1VDDPowerPower supply
W24P1.02Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
Y2VDDHPowerHigh voltage power supply
Y23P1.01Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
AA24SWDCLKDebugSerial wire debug clock input for debug and programming
AB2N.C.
AC5DECUSBPowerUSB 3.3 V regulator supply decoupling
AC9P0.14Digital I/OGeneral purpose I/O
AC11P0.16Digital I/OGeneral purpose I/O
AC13

P0.18

nRESET

Digital I/O

General purpose I/O

Configurable as pin RESET

AC15N.C.
AC17P0.21Digital I/OGeneral purpose I/O
AC19N.C.
AC21N.C.
AC24SWDIODebugSerial wire debug I/O for debug and programming
AD2VBUSPower5 V input for USB 3.3 V regulator
AD4D-USBUSB D-
AD6D+USBUSB D+
AD8P0.13Digital I/OGeneral purpose I/O
AD10P0.15Digital I/OGeneral purpose I/O
AD12P0.17Digital I/OGeneral purpose I/O
AD14VDDPowerPower supply
AD16P0.20Digital I/OGeneral purpose I/O
AD18P0.22Digital I/OGeneral purpose I/O
AD20P0.24Digital I/OGeneral purpose I/O
AD22

P1.00

TRACEDATA0

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[0]

Serial wire output (SWO)

AD23VDDPowerPower supply
Die padVSSPowerGround padExposed die pad must be connected to ground (VSS) for proper device operation
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.
Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P0.27, P1.08, P0.04, and P1.09.

QFN40 pin assignments

The pin assignment figure and table describe the assignments for this variant of the chip.

Figure 2. QFN40 pin assignments, top view


Table 2. QFN40 pin assignments
PinNameFunctionDescriptionRecommended usage
Left side of the chip
1DEC1Power1.1 V Digital supply decoupling
2

P0.00

XL1

Digital I/O

Analog input

General purpose I/O pin.

Connection for 32.768 kHz crystal

3

P0.01

XL2

Digital I/O

Analog input

General purpose I/O pin

Connection for 32.768 kHz crystal

4

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O pin

Analog input

5

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O pin

Analog input

6P1.09Digital I/OGeneral purpose I/O pin
7P0.11Digital I/OGeneral purpose I/O pin
8VDDPowerPower supply
9VDDHPowerHigh voltage power supply
10VBUSPower5 V input for USB 3.3 V regulator
Bottom side of the chip
11DECUSBPowerUSB 3.3 V regulator supply decoupling
12D-USBUSB D-
13D+USBUSB D+
14P0.15Digital I/OGeneral purpose I/O
15P0.17Digital I/OGeneral purpose I/O
16

P0.18

nRESET

Digital I/O

General purpose I/O

Configurable as pin RESET

17P0.20Digital I/OGeneral purpose I/O
18VDDPowerPower supply
19SWDIODebugSerial wire debug I/O for debug and programming
20SWDCLKDebugSerial wire debug clock input for debug and programming
Right side of the chip
21

DEC5

Not connected

Power

1.3 V regulator supply decoupling for build codes Axx and earlier.

Not connected for build codes Bxx and later.

22

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

Standard drive, low frequency I/O only
23

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

Standard drive, low frequency I/O only
24ANTRFSingle-ended radio antenna connectionSee Reference circuitry for guidelines on how to ensure good RF performance
25VSS_PAPowerGround (radio supply)
26DEC6Power1.3 V regulator supply decouplingMust be connected to DEC4 (pin 38)
27DEC3PowerPower supply, decoupling
28XC1Analog inputConnection for 32 MHz crystal
29XC2Analog inputConnection for 32 MHz crystal
30VDDPowerPower supply
Top side of the chip
31

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
32

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
33

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
34

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
35

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
36

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O pin

Analog input

37VSSPowerGround
38DEC4Power1.3 V regulator supply decouplingMust be connected to DEC6 (pin 26)
39DCCPowerDC/DC converter output
40VDDPowerPower supply
Backside of the the chip
Die padVSSPowerGround padExposed die pad must be connected to ground (VSS) for proper device operation
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.
Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P1.09, P0.04, and P0.31.

WLCSP ball assignments

The ball assignment figure and table describe the assignments for this variant of the chip.

Figure 3. WLCSP ball assignments, top view

WLCSP ball assignments

Table 3. WLCSP ball assignments
PinNameFunctionDescriptionRecommended usage
A1XC1Analog inputConnection for 32 MHz crystal
A2XC2Analog inputConnection for 32 MHz crystal
A3P0.25Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
A4

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
A5

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
A6DEC4Power1.3 V regulator supply decouplingMust be connected to DEC6 (ball C2)
A7VSSPowerGround
A8DCCPowerDC/DC converter output
A9VDDPowerPower supply
B3VDDPowerPower supply
B4P1.03Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
B5

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
B6

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
B7

P0.01

XL2

Digital I/O

Analog input

General purpose I/O pin

Connection for 32.768 kHz crystal

B8

P0.00

XL1

Digital I/O

Analog input

General purpose I/O pin.

Connection for 32.768 kHz crystal

B9DEC1Power1.1 V Digital supply decoupling
C1VSS_PAPowerGround (radio supply)
C2DEC6Power1.3 V regulator supply decouplingMust be connected to DEC4 (ball A6)
C4P1.05Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
C5P0.19Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
C6

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
C7

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O pin

Analog input

Standard drive, low frequency I/O only
C8P0.27Digital I/OGeneral purpose I/O
C9P0.26Digital I/OGeneral purpose I/O
D3VSSPowerGround
D4VSSPowerGround
D5VSSPowerGround
D6VSSPowerGround
D7P0.23Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
D8

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O pin

Analog input

D9

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O pin

Analog input

E1ANTRFSingle-ended radio antenna connectionSee Reference circuitry for guidelines on how to ensure good RF performance
E2

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

Standard drive, low frequency I/O only
E3P1.06Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
E4VSSPowerGround
E5VSSPowerGround
E6VSSPowerGround
E7P0.08Digital I/OGeneral purpose I/O
E8

P0.07

TRACECLK

Digital I/O

Trace clock

General purpose I/O

Trace buffer clock

E9P0.06Digital I/OGeneral purpose I/O
F1

DEC5

Not connected

Power

1.3 V regulator supply decoupling for build codes Axx and earlier.

Not connected for build codes Bxx and later.

F2

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

Standard drive, low frequency I/O only
F3P1.01Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
F4VSSPowerGround
F5VSSPowerGround
F6VSSPowerGround
F7P0.13Digital I/OGeneral purpose I/O
F8

P1.09

TRACEDATA3

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[3]

F9P1.08Digital I/OGeneral purpose I/O
G1P1.07Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
G2P1.04Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
G3P0.24Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
G4P0.21Digital I/OGeneral purpose I/O
G5P0.20Digital I/OGeneral purpose I/O
G6P0.16Digital I/OGeneral purpose I/O
G8

P0.11

TRACEDATA2

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[2]

G9VDDPowerPower supply
H1P1.02Digital I/OGeneral purpose I/OStandard drive, low frequency I/O only
H2SWDCLKDebugSerial wire debug clock input for debug and programming
H3

P1.00

TRACEDATA0

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[0]

Serial wire output (SWO)

H4

P0.18

nRESET

Digital I/O

General purpose I/O

Configurable as pin RESET

H5P0.15Digital I/OGeneral purpose I/O
H6

P0.12

TRACEDATA1

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[1]

H7D-USBUSB D-
H8VBUSPower5 V input for USB 3.3 V regulator
H9VDDHPowerHigh voltage power supply
J1VDDPowerPower supply
J2SWDIODebugSerial wire debug I/O for debug and programming
J3P0.22Digital I/OGeneral purpose I/O
J4VDDPowerPower supply
J5P0.17Digital I/OGeneral purpose I/O
J6P0.14Digital I/OGeneral purpose I/O
J7D+USBUSB D+
J8DECUSBPowerUSB 3.3 V regulator supply decoupling
J9VSSPowerGround
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.
Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P0.27, P1.08, P0.04, and P1.09.