Current consumption

Because the Power Management Unit (PMU) is constantly adjusting the different power and clock sources, estimating an application's current consumption can be challenging when the measurements cannot be performed directly on the hardware. To facilitate the estimation process, a set of current consumption scenarios is provided to show the typical current drawn from the VDD or VDDH supply.

Each scenario specifies a set of operations and conditions applying to the given scenario. All scenarios are listed in Electrical specification. The following table shows a set of common conditions used in all scenarios, unless otherwise stated in the description of a given scenario.

Table 1. Current consumption scenarios, common conditions
ConditionValueNote
Supply3 V on VDD/VDDH (normal voltage mode)
Temperature25°C
CPUWFI (wait for interrupt)/WFE (wait for event) sleep
PeripheralsAll idle
ClockHFCLK=HFINT running at 64 MHz

LFCLK=Not running

RegulatorDC/DC on VREGMAIN, VREGRADIO, and VREGH (when used)
Application core RAM8 kBIn System ON, RAM value refers to the amount of RAM that is switched on. The remainder of RAM is non retained. In System OFF, RAM value refers to amount of RAM that is retained.
Network core RAM0 kB
Cache enabledYesOnly applies when the CPU is running from flash memory.
Network core forced offYes
32 MHz crystalSMD 2016

32 MHz

ftol= ±30 ppm

CL=8 pF

RS≤50 Ω

DL≤100 μW

Only applies when the high frequency crystal oscillator (HFXO) is running. HFXO is used when the radio is running.
32 kHz crystalSMD 2012

32.768 kHz

ftol= ±20 ppm

CL=9 pF

C0=1.3 pF

RL=70 kΩ

DL≤1.0 μW

Only applies when the low frequency crystal oscillator (LFXO) is running.
InductorsSMD 1608

L = 10 μH

Tol = 20%

Isat ≥ 90 mA

RDC ≤ 1.2 Ω

Compiler versionGCC version 7.3.1 20180622 (arm-none-eabi-gcc)
Compiler flags-mcpu=cortex-m33 -mthumb -mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16 -fno-delete-null-pointer-checks -fmax-errors=1 -funroll-all-loops -ffunction-sections -falign-functions=16 -fno-strict-aliasing -O3

Electrical specification

Sleep

SymbolDescriptionMin.Typ.Max.Units
ION_IDLE1

System ON, 0 kB application RAM, wake on any event

1.3uA
ION_IDLE1,LDO

System ON, 0k application RAM, wake on any event, regulator = LDO

3.3uA
ION_IDLE2

System ON, wake on any event

1.3uA
ION_IDLE2,LDO

System ON, wake on any event, regulator = LDO

3.4uA
ION_IDLE3

System ON, wake on any event, power-fail comparator enabled

1.3uA
ION_IDLE3,128MHz

System ON, wake on any event, power-fail comparator enabled, clock=HFINT128M

785uA
ION_IDLE4

System ON, wake on GPIOTE input (event mode, LATENCY=LowLatency)

48uA
ION_IDLE4_LP

System ON, wake on GPIOTE input (event mode, LATENCY=LowPower)

1.3uA
ION_IDLE5

System ON, wake on GPIOTE PORT event

1.3uA
ION_IDLE6

System ON, 0 kB application RAM, wake on RTC (running from LFXO clock)

1.5uA
ION_IDLE7

System ON, wake on RTC (running from LFXO clock)

1.5uA
ION_IDLE8

System ON, 0 kB application RAM, wake on RTC (running from LFXO clock), 5 V supply on VDDH, VREGH output = 3.3 V

1.7uA
ION_IDLE7

System ON, 0 kB network RAM, wake on network RTC (running from LFXO clock)

1.5uA
ION_IDLE8

System ON, 64 kB network RAM, wake on network RTC (running from LFXO clock)

1.7uA
ION_IDLE9

System ON, 0 kB application RAM, wake on RTC (running from LFRC clock)

2.1uA
ION_IDLE10

Both cores in System ON, wake on any event. VREQH=Disabled.

1.3uA
ION_IDLE10_VREQH

Both cores in System ON, wake on any event. VREQH=Enabled.

1.4uA
IOFF0

System OFF, 0 kB application RAM, wake on reset

1.0uA
IOFF0,LDO

System OFF, 0 kB application RAM, wake on reset; regulator = LDO

1.4uA
IOFF1

System OFF, 0 kB application RAM, wake on LPCOMP

0.9uA
IOFF2

System OFF, wake on reset

0.9uA
IOFF3

System OFF, 0 kB application RAM, wake on reset, 5 V supply on VDDH, VREGH output = 3.3V

1.1uA
IOFF3,LDO

System OFF, 0 kB application RAM, wake on reset, 5 V supply on VDDH, VREGH output = 3.3V; regulator = LDO

1.4uA
IOFF4

System OFF, 512 kB application RAM + 64 kB network RAM, wake on reset

2.4uA
Figure 1. System OFF, 0 kB application RAM, wake on reset (typical values)
Figure 2. System ON, wake on any event, power-fail comparator enabled (typical values)

Application CPU running

The application CPU running parameters are obtained using the following compiler version:

Compiler: Arm version 6.14 (armclang)

Compiler flags:
-std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -fno-rtti -flto -funsigned-char -mcmse -Omax -ffunction-sections
Linker flags:
-Omax

20 kB of RAM in application core switched on and retained in execute-from-flash cases, and 44 kB in execute-from-RAM cases.

SymbolDescriptionMin.Typ.Max.Units
IAPPCPU0

CPU running CoreMark from flash, regulator = LDO, clock = HFINT128M

15.5mA
IAPPCPU2

CPU running CoreMark from flash, clock = HFXO128M

8.0mA
IAPPCPU3

CPU running CoreMark from flash, clock = HFXO64M

3.6mA
IAPPCPU4

CPU running CoreMark from flash, clock = HFINT128M

7.8mA
IAPPCPU5

CPU running CoreMark from flash

3.3mA
IAPPCPU8

CPU running CoreMark from RAM, clock = HFINT128M

7.9mA
IAPPCPU9

CPU running CoreMark from RAM

3.4mA
IAPPCPU10

CPU running CoreMark from RAM, clock = HFXO128M

8.2mA
IAPPCPU11

CPU running CoreMark from RAM, clock = HFXO64M

3.6mA

Network CPU running

The network CPU running parameters are obtained using the following compiler version:

Compiler: Arm version 6.14 (armclang)

Compiler flags: -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m33+nodsp -mfpu=none -mfloat-abi=soft -fno-rtti -flto -funsigned-char -Omax -ffunction-sections
Linker flags:
-Omax

20 kB of RAM in network core switched on and retained in execute-from-flash cases, and 40 kB in execute-from-RAM cases.

Clock and regulator settings only apply to network core. The settings in the application core are the same as the common conditions.

SymbolDescriptionMin.Typ.Max.Units
INETCPU0

CPU running CoreMark from flash, regulator = LDO

5.1mA
INETCPU1

CPU running CoreMark from flash

2.4mA
INETCPU2

CPU running CoreMark from flash, clock = HFXO64M

2.6mA
INETCPU3

CPU running CoreMark from RAM, regulator = LDO

4.3mA
INETCPU4

CPU running CoreMark from RAM

2.0mA
INETCPU5

CPU running CoreMark from RAM, clock = HFXO64M

2.2mA

COMP active

SymbolDescriptionMin.Typ.Max.Units
ICOMP,LP

COMP enabled, Low-power mode

60uA
ICOMP,NORM

COMP enabled, normal mode

62uA
ICOMP,HS

COMP enabled, High-speed mode

68uA

I2S active

SymbolDescriptionMin.Typ.Max.Units
II2S0

I2S transferring data @ 2 x 16 bit x 16 kHz (CONFIG.MCKFREQ = 32MDIV63, CONFIG.RATIO = 32X), clock = HFXO64M

2000uA
II2S1

I2S transferring data @ 2 x 16 bit x 16 kHz (CONFIG.MCKFREQ = 510000, CONFIG.RATIO = 32X), clock = HFXO ACLK @ 12.288 MHz

2170uA
II2S2

I2S transferring data @ 2 x 16 bit x 48 kHz (CONFIG.MCKFREQ = 505286656, CONFIG.RATIO = 32X), clock = HFXO ACLK @ 12.288 MHz

2310uA

LPCOMP active

SymbolDescriptionMin.Typ.Max.Units
ILPCOMP,EN

LPCOMP enabled

45uA

NFCT active

SymbolDescriptionMin.Typ.Max.Units
ISENSE

System ON, current in SENSE STATE (this current does not apply when in NFC field)

1.3uA
IACTIVATED

System ON, current in ACTIVATED STATE, clock = HFXO64M

1080uA

PDM active

SymbolDescriptionMin.Typ.Max.Units
IPDM,RUN

PDM receiving and processing data @ 1 MHz (RATIO = 64, PDMCLKCTRL = 135274496), stereo mode, clock = HFXO64M

655uA
IPDM,RUN,ACLK

PDM receiving and processing data @ 1 MHz (RATIO = 64, PDMCLKCTRL = 343597056), stereo mode, HFXO ACLK = 12.288 MHz

1045uA

PWM active

SymbolDescriptionMin.Typ.Max.Units
IPWM,RUN0

PWM running at 125 kHz, top = 10, duty = 50%

560uA
IPWM,RUN1

PWM running at 16 MHz, top = 10, duty = 50%

560uA
IPWM,RUN1,LDO

PWM running at 16 MHz, top = 10, duty = 50%; regulator = LDO

1035uA
IPWM,RUN2

PWM running at 125 kHz, top = 10, duty = 50%, clock = HFXO64M

750uA
IPWM,RUN3

PWM running at 16 MHz, top = 10, duty = 50%, clock = HFXO64M

755uA

QDEC active

SymbolDescriptionMin.Typ.Max.Units
IQDEC,RUN

QDEC running

480uA

QSPI active

SymbolDescriptionMin.Typ.Max.Units
IQSPI,IDLE

QSPI idle (enabled, but not activated)

45uA
IQSPI,ACTIVE

QSPI active (activated, but not transferring data)

1790uA
IQSPI,DATA

QSPI transferring data (activated, and transferring data to/from external flash memory), SCKFREQ = 96 MHz, quad mode, clock = HFXO192M

4430uA

RADIO transmitting/receiving

64 kB of network core RAM switched on and retained.

Clock and regulator settings only apply to network core. The settings in the application core are the same as the common conditions.

SymbolDescriptionMin.Typ.Max.Units
IRADIO_TX0

Radio transmitting @ +3 dBm output power, 1 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M

5.3mA
IRADIO_TX1

Radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M

4.1mA
IRADIO_TX2

Radio transmitting @ -40 dBm output power, 1 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M

2.6mA
IRADIO_TX3

Radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M; regulator = LDO

9.7mA
IRADIO_TX4

Radio transmitting @ -40 dBm output power, 1 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M; regulator = LDO

5.0mA
IRADIO_TX5

Radio transmitting @ 0 dBm output power, 2 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M

4.2mA
IRADIO_TX6

Radio transmitting @ 0 dBm output power, 500 kbps Bluetooth low energy (BLE) long-range (LR) mode, clock = HFXO64M

4.1mA
IRADIO_TX7

Radio transmitting @ 0 dBm output power, 125 kbps Bluetooth low energy (BLE) long-range (LR) mode, clock = HFXO64M

4.1mA
IRADIO_TX8

Radio transmitting @ 0 dBm output power, 250 kbps IEEE 802.15.4-2006 mode, clock = HFXO64M

4.1mA
IRADIO_RX0

Radio receiving @ 1 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M

3.7mA
IRADIO_RX1

Radio receiving @ 1 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M; regulator = LDO

8.0mA
IRADIO_RX2

Radio receiving @ 2 Mbps Bluetooth low energy (BLE) mode, clock = HFXO64M

4.1mA
IRADIO_RX3

Radio receiving @ 500 kbps Bluetooth low energy (BLE) long-range (LR) mode, clock = HFXO64M

3.6mA
IRADIO_RX4

Radio receiving @ 125 kbps Bluetooth low energy (BLE) long-range (LR) mode, clock = HFXO64M

3.6mA
IRADIO_RX5

Radio receiving @ 250 kbps IEEE 802.15.4-2006 mode, clock = HFXO64M

3.9mA
Figure 3. Radio transmitting at 3 dBm output power, 1 Mbps Bluetooth LE mode (typical values)
Figure 4. Radio transmitting at 0 dBm output power, 1 Mbps Bluetooth LE mode (typical values)

RNG active

SymbolDescriptionMin.Typ.Max.Units
IRNG0

RNG running, 64 kB network RAM

270uA

SAADC active

SymbolDescriptionMin.Typ.Max.Units
ISAADC,RUN

SAADC sampling @ 16 ksps, acquisition time = 20 us, clock = HFXO64M

980uA
ISAADC,TASK

SAADC sampling @ 1 kHz from RTC in task mode, acquisition time = 20 us, clock = HFINT64M and LFXO

160uA

TEMP active

SymbolDescriptionMin.Typ.Max.Units
ITEMP0

TEMP started, 64 kB network RAM

615uA

TIMER running

SymbolDescriptionMin.Typ.Max.Units
ITIMER0

One TIMER running @ 1 MHz

475uA
ITIMER1

One TIMER running @ 1 MHz, clock = HFXO64M

670uA
ITIMER2

One TIMER running @ 16 MHz

560uA
ITIMER2,LDO

One TIMER running @ 16 MHz; regulator = LDO

1040uA
ITIMER3

One TIMER running @ 16 MHz, clock = HFXO64M

750uA
ITIMER3,LDO

One TIMER running @ 16 MHz, clock = HFXO64M; regulator = LDO

1280uA
ITIMER4

One TIMER running @ 16 MHz, clock = HFINT128M

750uA
INET,TIMER0

One network TIMER running @ 1 MHz

170uA
INET,TIMER1

One network TIMER running @ 1 MHz, clock = HFXO64M

400uA
INET,TIMER2

One network TIMER running @ 16 MHz

220uA
INET,TIMER3

One network TIMER running @ 16 MHz, clock = HFXO64M

445uA

SPIM active

SymbolDescriptionMin.Typ.Max.Units
ISPIM0

SPIM transferring data @ 2 Mbps

935uA
ISPIM1

SPIM transferring data @ 2 Mbps, clock = HFXO64M

1145uA
ISPIM2

SPIM transferring data @ 8 Mbps

1705uA
ISPIM3

SPIM transferring data @ 8 Mbps, clock = HFXO64M

1930uA
ISPIM4

SPIM transferring data @ 32 Mbps

2115uA
ISPIM5

SPIM transferring data @ 32 Mbps, clock = HFXO64M

2345uA

SPIS active

SymbolDescriptionMin.Typ.Max.Units
ISPIS0

SPIS configured and idle (enabled, no CSN activity)

145uA
ISPIS1

SPIS transferring data @ 2 Mbps

713uA
ISPIS2

SPIS transferring data @ 2 Mbps, clock = HFXO64M

913uA

TWIM active

SymbolDescriptionMin.Typ.Max.Units
ITWIM0

TWIM transferring data @ 100 kbps

965uA
ITWIM1

TWIM transferring data @ 100 kbps, clock = HFXO64M

1170uA
ITWIM2

TWIM transferring data @ 400 kbps

1000uA
ITWIM3

TWIM transferring data @ 400 kbps, clock = HFXO64M

1205uA
ITWIM4

TWIM transferring data @ 1000 kbps

2050uA
ITWIM5

TWIM transferring data @ 1000 kbps, clock = HFXO64M

2295uA

TWIS active

SymbolDescriptionMin.Typ.Max.Units
ITWIS,IDLE

TWIS configured and enabled (IDLE state)

45uA
ITWIS0

TWIS transferring data @ 100 kbps

945uA
ITWIS1

TWIS transferring data @ 400 kbps

985uA
ITWIS2

TWIS transferring data @ 100 kbps, clock = HFXO64M

1150uA
ITWIS3

TWIS transferring data @ 400 kbps, clock = HFXO64M

1185uA

UARTE active

SymbolDescriptionMin.Typ.Max.Units
IUARTE,IDLE0

UARTE RX idle (started, waiting for data, no data transfer)

645uA
IUARTE,IDLE1

UARTE RX idle (started, waiting for data, no data transfer), clock = HFXO64M

840uA
IUARTE0

UARTE transferring data @ 1200 bps, clock = HFXO64M

885uA
IUARTE1

UARTE transferring data @ 115200 bps, clock = HFXO64M

890uA
IUARTE2

UARTE receiving data @ 115200 bps, clock = HFXO64M

890uA
IUARTE3

UARTE transmitting and receiving data @ 115200 bps, clock = HFXO64M

895uA

WDT active

SymbolDescriptionMin.Typ.Max.Units
IWDT,APP

Application MCU WDT started

2.0uA
IWDT,APP,LDO

Application MCU WDT started; regulator = LDO

4.9uA
IWDT,NET

Network MCU WDT started, 64 kB network RAM

3.2uA

Compounded

These are scenarios where both cores are active. 20 kB of RAM in the application core and 64 kB of RAM in the network core are switched on and retained.

In scenarios where both cores are active, the clock and regulator settings apply to both.

SymbolDescriptionMin.Typ.Max.Units
IS0

Application CPU running CoreMark from flash, radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M

7.3mA
IS1

Application CPU running CoreMark from flash, radio receiving @ 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M

6.9mA
IS2

Application CPU running CoreMark from flash, radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M, regulator = LDO

16.9mA
IS3

Application CPU running CoreMark from flash, radio receiving @ 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M; regulator = LDO

15.6mA
IS4

Application CPU running CoreMark from flash, radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M, 5 V supply on VDDH, VREGH output = 3.3 V

6.7mA
IS5

Application CPU running CoreMark from flash, radio receiving @ 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M, 5 V supply on VDDH, VREGH output = 3.3 V

6.4mA
IS6

Network CPU running CoreMark from flash, radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth Low Energy mode, clock = HFXO64M

5.9mA
IS7

Network CPU running CoreMark from flash, radio receiving @ 1 Mbps Bluetooth Low Energy mode, clock = HFXO64M

5.4mA
IS8

Application + Network CPU running CoreMark from flash, radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M

9.1mA
IS9

Application + Network CPU running CoreMark from flash, radio receiving @ 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M

8.6mA
IS10

Application + Network CPU running CoreMark from flash, radio transmitting @ +3 dBm output power, 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M

9.9mA
IS11

Application + Network CPU running CoreMark from flash, radio transmitting @ +3 dBm output power, 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M; regulator = LDO

21.5mA
IS12

Application + Network CPU running CoreMark from flash, radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M; regulator = LDO

20.2mA
IS13

Application + Network CPU running CoreMark from flash, radio receiving @ 1 Mbps Bluetooth Low Energy mode; clock = HFXO64M; regulator = LDO

21.5mA
IS14

Network CPU running CoreMark from flash, radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth Low Energy mode, clock = HFXO64M; regulator = LDO

12.6mA
IS15

Network CPU running CoreMark from flash, radio receiving @ 1 Mbps Bluetooth Low Energy mode, clock = HFXO64M; regulator = LDO

14.0mA

USBD active

SymbolDescriptionMin.Typ.Max.Units
IUSB,ACTIVE,VBUS

Current from VBUS supply, USB active

1.2mA
IUSB,SUSPEND,VBUS

Current from VBUS supply, USB suspended, CPU sleeping

180uA
IUSB,ACTIVE,VDD

Current from VDD supply (normal voltage mode), all RAM retained, CPU running, USB active

3.0mA
IUSB,SUSPEND,VDD

Current from VDD supply (normal voltage mode), all RAM retained, CPU sleeping, USB suspended

815uA
IUSB,SUSPEND,VDD,LDO

Current from VDD supply (normal voltage mode), all RAM retained, CPU sleeping, USB suspended, regulator = LDO

135uA
IUSB,ACTIVE,VDDH

Current from VDDH supply (high voltage mode), VDD=3 V (VREGH output), all RAM retained, CPU running, USB active

3.2mA
IUSB,SUSPEND,VDDH

Current from VDDH supply (high voltage mode), VDD=3 V (VREGH output), all RAM retained, CPU sleeping, USB suspended

2340uA
IUSB,SUSPEND,VDDH,LDO

Current from VDDH supply (high voltage mode), VDD=3 V (VREGH output), all RAM retained, CPU sleeping, USB suspended, regulator = LDO

125uA
IUSB,DISABLED,VDD

Current from VDD supply, USB disabled, VBUS supply connected, all RAM retained, CPU sleeping

3uA