RESET — Reset control

A reset in the system is triggered by either a system-level or core-level reset source.

A system-level reset resets all cores. Power-on reset, brownout reset, and pin reset are examples of a system-level reset. A core-level reset, such as a soft reset or a lockup, resets either the entire core or only part of it. The different reset sources in the system are illustrated in the following figure.

Reset resources — Figure 1. Reset sources

After a system-level reset, the application core starts up on its own. The network core is not automatically started, but can be started by the application core CPU, see Network Force-OFF.

After a reset occurs, the register RESETREAS can be read to determine which source generated the reset. Each core has its own RESETREAS register. System-level and application core reset sources are also available in the network core's RESETREAS register, unless otherwise noted.

Power-on reset

The power-on reset (POR) generator initializes the system when the VDD supply voltage is above the power-on threshold. This also applies in high voltage mode, where the VDD supply voltage is provided by the high voltage regulator (VREGH).

The system is held in a reset state until the supply has reached the minimum operating voltage, and the internal voltage regulators have started. After a power-on reset, the application core is started while the network core is held in reset, see Network Force-OFF.

Pin reset

A pin reset is generated when the physical reset pin on the device is asserted.

Similar to a power-on reset, the application core is started after the reset pin is deasserted. The network core is held in reset, see Network Force-OFF.

The reset pin has an internal pull-up resistor with the same resistance as GPIO pull-ups, see GPIO — General purpose input/output.

Brownout reset

The brownout reset (BOR) generator puts the system in reset state if the VDD supply voltage drops below the brownout reset threshold. This also applies in high voltage mode, where the VDD supply voltage is provided by the high voltage regulator (VREGH).

Similar to a power-on reset, the application core is started after BOR is deasserted while the network core is held in reset, see Network Force-OFF.

Wakeup from System OFF mode reset

The device is reset when it wakes up from System OFF mode.

Similar to a power-on reset, the application core is started while the network core is held in reset, see Network Force-OFF.

If the device is in Debug Interface mode, the debug access port (DAP) is not reset after a wakeup from System OFF. For more information, see Debug and trace.

Soft reset

Soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR) in the Arm® core is set. For more information, see Arm documentation.

When the application core performs a soft reset, the network core is held in reset, see Network Force-OFF. A soft reset in the network core will only cause the network core to reset.

A soft reset can also be generated using the RESET register in the associated CTRL-AP.

Watchdog timer reset

A watchdog timer (WDT) reset is generated when the watchdog timer times out.

Each core has its own WDT instance. When the application core gets a WDT reset, the network core is held in reset, see Network Force-OFF. A WDT reset in the network core will only cause the network core to reset. The reset target depends on the core where WDT is instantiated.

Note: Because the network core WDT reset is local for the network core, the application core is not aware of WDT timing out in the network core. Notifying the application core is possible. One way is to check the register RESETREAS for WDT flags and report the error through inter-processor communication (IPC).

For more information about WDT, see WDT — Watchdog timer. More information about IPC is available in IPC — Interprocessor communication.

Network Force-OFF

The application core can force the network core off.

The application core can hold the network core in Force-OFF mode, using register NETWORK.FORCEOFF.

Application core resets implicitly result in the network core being held in Force-OFF. The network core will be held in Force-OFF until the application core releases it using the NETWORK.FORCEOFF register.

For details on how to use this mode, see Force-OFF mode.

Retained registers

A retained register is one that retains its value in System OFF and/or Force-OFF modes and when reset, depending on the reset source. See individual peripheral chapters for information about which registers are retained for the various peripherals.

Application core reset behavior

Application core reset behavior depends on the reset source.

Any reset in the application core will cause a network core Force-OFF, triggering the FORCEOFF reset source in the network core. For more information, see Network Force-OFF.

In System OFF mode, the watchdog timer is not running and there is no CPU lockup possible. RAM may be fully or partially retained, depending on RAM retention settings in VMC — Volatile memory controller.

If the device is in Debug Interface mode, the debug components will not be reset. Additionally, CPU lockup will not generate a reset. See Debug and trace for more information about the different debug components in the system.

Application core reset targets and their reset sources are summarized in the following table.

Table 1. Application core reset targets and their reset sourcesAn 'x' in the table means that the specific module is reset.
Reset source	Reset target
Reset source	CPU	Network core	Debug	RAM	WDT	RESETREAS
CPU lockup	x	x
Soft reset	x	x
Wakeup from System OFF mode reset	x	x	x	x^¹	x
Watchdog timer reset	x	x	x	x	x
Pin reset	x	x	x	x	x
Brownout reset	x	x	x	x	x	x
Power-on reset	x	x	x	x	x	x
NETWORK.FORCEOFF		x

Note: RAM is never reset, but depending on the reset source, its content may be corrupted.

Some retained registers may have a different reset behavior, as shown in the following table.

Table 2. Application core reset behavior for retained registersAn 'x' in the table means that the specific module is reset.
Reset source	Reset target
Reset source	Regular peripheral registers	SPU	GPIO	REGULATORS, OSCILLATORS	POWERGPREGRET
CPU lockup	x	x	x^²
Soft reset	x	x	x^²
Wakeup from System OFF mode reset	x
Watchdog timer reset	x	x	x	x
Pin reset	x	x	x	x
Brownout reset	x	x	x	x	x
Power-on reset	x	x	x	x	x

Network core reset behavior

Network core reset behavior depends on the reset source.

In System OFF mode, or when the network core is held in Force-OFF, the watchdog timer is not running and there is no CPU lockup possible. RAM may be fully or partially retained, depending on RAM retention settings in VMC — Volatile memory controller.

Any reset in the application core will cause a network core force off, triggering the network FORCEOFF reset source in the following table. For more information, see Network Force-OFF.

Table 3. Network core reset target sourcesAn 'x' in the table means that the specific module is reset. Pin reset, brownout reset, and power-on reset are system level reset sources with the network core and application core having the same behavior, see Application core reset behavior.
Reset source	Reset target
Reset source	CPU	RAM	WDT	RESETREAS
CPU lockup	x
Soft reset	x
Network FORCEOFF	x	x^³	x
Application Watchdog timer reset	x	x	x
Local Watchdog timer reset	x	x	x

Note: RAM is never reset, but its content may be corrupted depending on the reset source.

Some retained registers may have a different reset behavior, as shown in following table.

Table 4. Network core reset behavior for retained registersAn 'x' in the table means that the specific module is reset. Pin reset, brownout reset, and power-on reset are system level reset sources with the network core and application core having the same behavior, see Application core reset behavior.
Reset source	Reset target
Reset source	Regular peripheral registers	GPIO	POWER.GPREGRET
CPU lockup	x	x ^⁴
Soft reset	x	x ^⁴
Network FORCEOFF	x
Application Watchdog timer reset	x	x
Local Watchdog timer reset	x	x

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
RESET : S RESET : NS	APPLICATION	0x50005000 0x40005000	US	S	NA	No	Reset control and status
RESET	NETWORK	0x41005000	HF	NS	NA	No	Reset status

Configuration


Instance	Domain	Configuration
RESET : S RESET : NS	APPLICATION	Not supported: LSREQ, LLOCKUP, LDOG, MRST, MFORCEOFF, LCTRLAP
RESET	NETWORK	Not supported: NETWORK.FORCEOFF

Register overview


Register	Offset	TZ	Description
RESETREAS	0x400		Reset reason
NETWORK.FORCEOFF	0x614		Force network core off

RESETREAS

Address offset: 0x400

Reset reason

Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing 1 to it. Multiple fields can be cleared at the same time by writing a value with several of the fields set to 1.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID								P	O	N	M	L					K	J	I									H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESETPIN										Reset from pin reset detected
			NotDetected	0								Not detected
			Detected	1								Detected
B	RW	DOG0										Reset from application watchdog timer 0 detected
			NotDetected	0								Not detected
			Detected	1								Detected
C	RW	CTRLAP										Reset from application CTRL-AP detected
			NotDetected	0								Not detected
			Detected	1								Detected
D	RW	SREQ										Reset from application soft reset detected
			NotDetected	0								Not detected
			Detected	1								Detected
E	RW	LOCKUP										Reset from application CPU lockup detected
			NotDetected	0								Not detected
			Detected	1								Detected
F	RW	OFF										Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO
			NotDetected	0								Not detected
			Detected	1								Detected
G	RW	LPCOMP										Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP
			NotDetected	0								Not detected
			Detected	1								Detected
H	RW	DIF										Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode
			NotDetected	0								Not detected
			Detected	1								Detected
I	RW	LSREQ										Reset from network soft reset detected Function present only in network core
			NotDetected	0								Not detected
			Detected	1								Detected
J	RW	LLOCKUP										Reset from network CPU lockup detected Function present only in network core
			NotDetected	0								Not detected
			Detected	1								Detected
K	RW	LDOG										Reset from network watchdog timer detected Function present only in network core
			NotDetected	0								Not detected
			Detected	1								Detected
L	RW	MFORCEOFF										Force-OFF reset from application core detected Function present only in network core
			NotDetected	0								Not detected
			Detected	1								Detected
M	RW	NFC										Reset after wakeup from System OFF mode due to NFC field being detected
			NotDetected	0								Not detected
			Detected	1								Detected
N	RW	DOG1										Reset from application watchdog timer 1 detected
			NotDetected	0								Not detected
			Detected	1								Detected
O	RW	VBUS										Reset after wakeup from System OFF mode due to VBUS rising into valid range
			NotDetected	0								Not detected
			Detected	1								Detected
P	RW	LCTRLAP										Reset from network CTRL-AP detected Function present only in network core
			NotDetected	0								Not detected
			Detected	1								Detected

NETWORK.FORCEOFF

Address offset: 0x614

Force network core off

Function present only in application core


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	FORCEOFF										Force network core off
			Release	0								Release Force-OFF
			Hold	1								Hold Force-OFF

Electrical specification

Application core startup times


Symbol	Description	Min.	Typ.	Max.	Units
t_POR	Time in power-on reset after supply reaches minimum operating voltage, depending on supply rise time.	..	..	..
t_POR,10us	VDD rise time 10 µs		0.7	1.0	ms
t_POR,10ms	VDD rise time > 10 ms		0		ms
t_PINR	Reset time when using pin reset, depending on pin capacitance	..	..	..
t_PINR,500nF	500 nF capacitance at reset pin		13	40	ms
t_PINR,10uF	10 µF capacitance at reset pin		260	800	ms
t_R2ON	Time from reset to ON (CPU execute)		t_POR + t_PINR
t_OFF2ON,NM	Time from OFF to CPU execute when in normal voltage mode (supply on VDD)		38		µs
t_{OFF2ON,LDO,HV}	Time from OFF to CPU execute when in high voltage mode (supply on VDDH) and VREGH using LDO regulator		38		µs
t_{OFF2ON,DCDC,HV}	Time from OFF to CPU execute when in high voltage mode (supply on VDDH) and VREGH using DC/DC regulator		38		µs
t_IDLE2CPU	Time from IDLE to CPU execute		23		µs
t_{IDLE2CPU,CONSTLAT}	Time from IDLE to CPU execute in constant latency submode		10		µs
t_EVTSET,CL1	Time from HW event to PPI event in Constant Latency System ON mode		62.5		ns
t_EVTSET,CL0	Time from HW event to PPI event in Low-Power System ON mode		62.5		ns

Network core startup times


Symbol	Description	Typ.	Units
t_{NET,EVTSET,CL1}	Time from HW event to PPI event in Constant Latency System ON mode	62.5	ns
t_{NET,EVTSET,CL0}	Time from HW event to PPI event in Low-Power System ON mode	62.5	ns
t_NET,IDLE2CPU	Time from IDLE to CPU execute	15	µs
t_{NET,IDLE2CPU,CONSTLAT}	Time from IDLE to CPU execute in constant latency submode	7	µs
t_FO2ON,NET64	Time for network core from OFF to CPU execute after NETWORK.FORCEOFF is released	20	µs

¹ Depending on RAM retention settings.

² Except MCUSEL field, the MCUSEL register of the GPIO peripheral is not reset for CPU lockup and Soft reset.

³ Depending on RAM retention settings.

⁴ MCUSEL settings are kept.