CPU
The Arm® Cortex®-M33 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a super set of 16- and 32-bit instructions to maximize code density and performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing including:
- Digital signal processing (DSP) instructions
- Single-cycle multiply and accumulate (MAC) instructions
- Hardware divide
- 8- and 16-bit single instruction multiple data (SIMD) instructions
- Single-precision floating-point unit (FPU)
- Memory Protection Unit (MPU)
- Arm TrustZone® for Armv8-M
The Arm Cortex Microcontroller Software Interface Standard (CMSIS) is implemented and available for the application processor.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).
Executing code from internal or external flash will have a wait state penalty. The instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see CACHE — Instruction/data cache. CPU performance parameters including wait states for different configurations, CPU current consumption and efficiency, and processing power and efficiency based on the CoreMark® benchmark can be found in Electrical specification.
Floating point interrupt
The floating point unit (FPU) may generate exceptions, for example, due to overflow or underflow. These exceptions may trigger interrupts when enabled in the FPU peripheral. For more information, see FPU — Floating point unit (FPU) exceptions.
Electrical specification
CPU performance
| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| WFLASH128 | CPU wait states, running CoreMark at 128 MHz from flash, cache disabled | 4 | |||
| WFLASHCACHE128 | CPU wait states, running CoreMark at 128 MHz from flash, cache enabled | 5 | |||
| WRAM128 | CPU wait states, running CoreMark at 128 MHz from RAM | 0 | |||
| WFLASH64 | CPU wait states, running CoreMark at 64 MHz from flash, cache disabled | 5 | |||
| WFLASHCACHE64 | CPU wait states, running CoreMark at 64 MHz from flash, cache enabled | 6 | |||
| WRAM64 | CPU wait states, running CoreMark at 64 MHz from RAM | 0 | |||
| CMFLASHCACHE128 | CoreMark, running from flash, cache enabled, HFXO128M | 514 | CoreMark | ||
| CMFLASH128/MHz | CoreMark per MHz, running from flash, cache enabled, HFXO128M | 4.0 | CoreMark/MHz | ||
| CMFLASH128/mA | CoreMark per mA, running from flash, cache enabled, DCDC 3 V, HFXO128M | 66 | CoreMark/mA | ||
| CMFLASHCACHE64 | CoreMark, running from flash, cache enabled, HFXO64M | 257 | CoreMark | ||
| CMFLASH64/MHz | CoreMark per MHz, running from flash, cache enabled, HFXO64M | 4.0 | CoreMark/MHz | ||
| CMFLASH64/mA | CoreMark per mA, running from flash, cache enabled, DCDC 3 V, HFXO64M | 72.5 | CoreMark/mA |
CPU and support module configuration
The Arm Cortex®-M33 processor has a number of CPU options and support modules implemented on the device.
| Option/Module | Description | Implemented |
|---|---|---|
| Core options | ||
| PRIORITIES | Priority bits | 3 |
| WIC | Wakeup Interrupt Controller | NO |
| Endianness | Memory system endianness | Little endian |
| DWT | Data Watchpoint and Trace | YES |
| Modules | ||
| MPU | Number of non-secure MPU regions | 8 |
| Number of secure MPU regions | 8 | |
| SAU | Number of SAU regions | 0 See SPU for more information about secure regions. |
| FPU | Floating-point unit | YES |
| DSP | Digital Signal Processing Extension | YES |
| Arm TrustZone® for Armv8-M | Armv8-M Security Extensions | YES |
| CPIF | Coprocessor interface | NO |
| ETM | Embedded Trace Macrocell | YES |
| ITM | Instrumentation Trace Macrocell | YES |
| MTB | Micro Trace Buffer | NO |
| CTI | Cross Trigger Interface | YES |
| BPU | Breakpoint Unit | YES |
| HTM | AHB Trace Macrocell | NO |