CPU

The Arm® Cortex®-M33 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a super set of 16- and 32-bit instructions to maximize code density and performance.

This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing including:

• Hardware divide
• 8- and 16-bit single instruction multiple data (SIMD) instructions
• Memory Protection Unit (MPU)

The Arm Cortex Microcontroller Software Interface Standard (CMSIS) is implemented and available for the application processor.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).

Executing code from internal or external flash will have a wait state penalty. The instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see NVMC — Non-volatile memory controller. CPU performance parameters including mode wait states, CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark can be found in Electrical specification.