UICR — User information configuration registers

The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user specific settings.

For information on writing registers, see NVMC — Non-volatile memory controller and Memory.

Any access, both read and write, to UICR must be a full 32-bit word aligned to a 32-bit address.

Registers


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
UICR	NETWORK	0x01FF8000	HF	NS	NA	No	User information configuration


Register	Offset	Description
APPROTECT	0x000	Access port protection
ERASEPROTECT	0x004	Erase protection
NRFFW[n]	0x200	Reserved for Nordic firmware design
CUSTOMER[n]	0x300	Reserved for customer

Address offset: 0x000

Access port protection


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PALL										Blocks debugger read/write access to all CPU registers and memory mapped addresses. Using any value except Unprotected will lead to the protection being enabled. Bits with value '1' can be written to '0'. Bits with value '0' cannot be written to '1'.
			Unprotected	0x50FA50FA								Unprotected
			Protected	0x00000000								Protected

Address offset: 0x004

Erase protection


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PALL										Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled.
			Unprotected	0xFFFFFFFF								Unprotected
			Protected	0x00000000								Protected

Address offset: 0x200 + (n × 0x4)

Reserved for Nordic firmware design


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	NRFFW										Reserved for Nordic firmware design

Address offset: 0x300 + (n × 0x4)

Reserved for customer


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	CUSTOMER										Reserved for customer