TAD - Trace and debug control

Configuration interface for trace and debug

Please refer to the Trace section for more information about how to configure the trace and debug interface.

Note: Although there are PSEL registers for the trace port, each function can only be mapped to a single pin due to pin speed requirements. Setting the PIN field to anything else will not have any effect. See Pin assignment chapter for more information

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
TAD	APPLICATION	0xE0080000	HF	S	NA	No	Trace and debug control

Register overview


Register	Offset	Description
CLOCKSTART	0x004	Start all trace and debug clocks.
CLOCKSTOP	0x008	Stop all trace and debug clocks.
ENABLE	0x500	Enable debug domain and aquire selected GPIOs
PSEL.TRACECLK	0x504	Pin configuration for TRACECLK
PSEL.TRACEDATA0	0x508	Pin configuration for TRACEDATA[0]
PSEL.TRACEDATA1	0x50C	Pin configuration for TRACEDATA[1]
PSEL.TRACEDATA2	0x510	Pin configuration for TRACEDATA[2]
PSEL.TRACEDATA3	0x514	Pin configuration for TRACEDATA[3]
TRACEPORTSPEED	0x518	Clocking options for the Trace Port debug interface Reset behavior is the same as debug components This register is retained.

CLOCKSTART

Address offset: 0x004

Start all trace and debug clocks.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	START
			Start	1								Start all trace and debug clocks.

CLOCKSTOP

Address offset: 0x008

Stop all trace and debug clocks.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	STOP
			Stop	1								Stop all trace and debug clocks.

ENABLE

Address offset: 0x500

Enable debug domain and aquire selected GPIOs


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE
			DISABLED	0								Disable debug domain and release selected GPIOs
			ENABLED	1								Enable debug domain and aquire selected GPIOs

PSEL.TRACECLK

Address offset: 0x504

Pin configuration for TRACECLK


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																											A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN										Pin number
			Traceclk	12								TRACECLK pin Note: Only this pin is valid
B	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.TRACEDATA0

Address offset: 0x508

Pin configuration for TRACEDATA[0]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																											A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN										Pin number
			Tracedata0	11								TRACEDATA0 pin Note: Only this pin is valid
B	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.TRACEDATA1

Address offset: 0x50C

Pin configuration for TRACEDATA[1]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																											A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN										Pin number
			Tracedata1	10								TRACEDATA1 pin Note: Only this pin is valid
B	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.TRACEDATA2

Address offset: 0x510

Pin configuration for TRACEDATA[2]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																											A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN										Pin number
			Tracedata2	9								TRACEDATA2 pin Note: Only this pin is valid
B	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.TRACEDATA3

Address offset: 0x514

Pin configuration for TRACEDATA[3]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																											A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN										Pin number
			Tracedata3	8								TRACEDATA3 pin Note: Only this pin is valid
B	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

TRACEPORTSPEED (Retained)

Address offset: 0x518

Clocking options for the Trace Port debug interface

Reset behavior is the same as debug components

This register is retained.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TRACEPORTSPEED										Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock.
			64MHz	0								Trace Port clock is: 64MHz
			32MHz	1								Trace Port clock is: 32MHz
			16MHz	2								Trace Port clock is: 16MHz
			8MHz	3								Trace Port clock is: 8MHz