AMBA interconnect (AMBIX)

The AMBA interconnect (AMBIX) is a multilayer-capable bus interconnect that provides low latency access from Managers to Subordinates.

Manager and Subordinate connections are arranged in Manager and Subordinate pairs, allowing for a sparse bus matrix. The interconnect supports multiple concurrent transactions when targeting different Subordinates.

Some peripherals do not have the opportunity to pause incoming data. Being a low priority bus manager might cause loss of data for such peripherals upon bus contention. To avoid bus contention when using multiple bus managers, follow these guidelines:

Avoid situations where more than one bus manager is accessing the same RAM subordinate.
If more than one bus manager is accessing the same RAM subordinate, make sure that the bus bandwidth is not exhausted.

The interconnect enforces the TrustZone® secure/non-secure attributes and is configured using MPC — Memory Privilege Controller.

AMBIX0 bus Managers and priority handling

The main interconnect (AMBIX0) has a bus matrix that handles bus arbitration.

AMBIX0 uses a round-robin bus Manager arbitration algorithm.

Some peripherals cannot pause incoming data. As a low priority bus Manager, data loss is possible for these peripherals when bus contention occurs. To avoid bus contention when using multiple bus Managers, follow these guidelines:

Avoid situations where more than one bus Manager is accessing the same RAM Subordinate.
If more than one bus Manager is accessing the same Subordinate, make sure that the bus bandwidth is not exhausted.

AMBIX0 override configuration

The main interconnect (AMBIX0) has a configurable bus matrix.

The overrides are used to configure the secure and non-secure memory regions in the device. They are also used to prevent or grant access to read, write, or execute from the memory region. For more details, see MPC — Memory Privilege Controller.