MEMCONF — Memory configuration

MEMCONF provides power control for RAM blocks.

Each RAM block can independently power up or power-down in System ON and System OFF mode. RAM blocks can contain multiple RAM sections. For more information about System ON and System OFF modes, see Power and clock management. For an overview of available RAM blocks and RAM sections, see Memory.

MEMCONF registers are used for configuring the following:

RAM sections to be retained during System OFF mode
RAM sections to be retained and accessible during System ON mode

In System OFF mode, a RAM section is retained by configuring the corresponding MEM[i] field of registers RET and RET2. The RET and RET2 registers control retention on half the address space within the memory block.

In System ON mode, retention and accessibility for a RAM section is configured in the corresponding MEM[i] field of register POWER[n].CONTROL (n=0..1).

The following table contains the complete list of blocks (RET.MEM[i], RET2.MEM[i].

Table 1. Memory block overview with MEMCONF.POWER configuration
Block number (index i in MEMCONF.POWER)	RAM section	RET reset value	RET2 reset value	CONTROL reset value
0	RAM00 section 0	1	x	1
1	RAM00 section 1	1	x	1
2	RAM00 section 2	1	x	1
3	RAM00 section 3	1	x	1
4	RAM01 section 0	1	x	1
5	RAM01 section 1	1	x	1
6	RAM01 section 2	1	x	1
7	RAM01 section 3	1	1	1
33	ICACHE tag + data 1:0	1	x	1
34	CRACEN PKEcode	1	x	1
35	CRACEN KeyRAM	1	x	1

A list of features that are retained using MEMCONF are found in the following table.

Table 2. Feature overview with MEMCONF.POWER.RET configuration
Block number (index i in MEMCONF.POWER)	Feature	RET reset value	Feature description
32	Restore VPR context at VPR reset	0	Enables the VPR context restore from the RAM at VPR reset, where the VPR reset maybe caused by a wakeup from hibernate. ^¹

The following table summarizes the behavior of the CONTROL and RET/RET2 fields when a power domain is powered on or off. The RAM section can be used to read and write data when it is powered. The RAM section is retained during System OFF.

Table 3. RAM section configuration
Configuration			RAM section status
Power mode	CONTROL	RET/RET2	Powered	Retained
System OFF	Any value	Off	No	No
System OFF	Off	On	No	No
System OFF	On	On	No	Yes
System ON IDLE	Off	Any value	No	No
System ON IDLE	On	Any value	No	Yes
System ON RUN	Any value	Any value	Yes	Yes

The advantage of not retaining RAM content is overall current consumption is reduced.

See chapter Memory for more information on RAM sections.

Note: CACHE — Instruction/data cache must be disabled when the ICACHE memory block is turned off, and only enabled after the ICACHE memory block is turned on.

¹ Must enable RAM retention using MEMCONF.POWER[0].RET2.MEM[7] to restore the VPR context correctly.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
MEMCONF : S MEMCONF : NS	GLOBAL	0x500CF000 0x400CF000	US	S	NA	No	Memory Configuration MEMCONF

Configuration


Instance	Domain	Configuration
MEMCONF : S MEMCONF : NS	GLOBAL

Register overview


Register	Offset	Description
POWER[n].CONTROL	0x500	Control memory block power.
POWER[n].RET	0x508	RAM retention for RAM [n].
POWER[n].RET2	0x50C	RAM retention for the second bank in the RAM block

POWER[n].CONTROL

Address offset: 0x500 + (n × 0x10)

Control memory block power.

Where n = 0 for memory blocks 0 to 31 and n = 1 for memory blocks 32 to 63.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A-f	RW	MEM[i] (i=0..31)										Keep the memory block MEM[i] on or off when in System ON mode. RAM blocks powered off this way will not be retained. All RAM blocks will be off in System OFF mode.
			Off	0								Power down
			On	1								Power up

POWER[n].RET

Address offset: 0x508 + (n × 0x10)

RAM retention for RAM [n].

Where n = 0 for RAM blocks 0 to 31 and n = 1 for RAM blocks 32 to 63.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A-f	RW	MEM[i] (i=0..31)										Keep the RAM block MEM[i] retained when in System OFF mode. All other RAM will be off in System OFF mode.
			Off	0								Retention off
			On	1								Retention on

POWER[n].RET2

Address offset: 0x50C + (n × 0x10)

RAM retention for the second bank in the RAM block

Where n = 0 for RAM blocks 0 to 31 and n = 1 for RAM blocks 32 to 63.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	RW	MEM[i] (i=0..31)										Keep the second bank in RAM block MEM[i] retained when in System OFF mode. All other RAM will be off in System OFF mode. Not all types of RAM blocks have two banks.
			Off	0								Retention off
			On	1								Retention on