POWER — Power control

The POWER peripheral provides an interface for the power and clock subsystem for task, event, and interrupt related settings.

The POWER peripheral requests resources from the power and clock subsystem. The power and clock subsystem makes sure that the power mode with the proper latency settings is selected when requested. This means that the Constant Latency mode is prioritized over Low-power mode. For an overview of power modes, see Sub-power modes.

The event POFWARN is a system level event that enables the device to react quickly if there is a power failure. The power-fail comparator must be configured and enabled to receive the event, see Power-fail comparator for more information.

Power control of the RAM blocks is controlled by the memory configuration peripheral (MEMCONF), see MEMCONF — Memory configuration.

Note: Registers INTEN, INTENSET, and INTENCLR are shared between the POWER and CLOCK peripherals.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
POWER : S POWER : NS	GLOBAL	0x5010E000 0x4010E000	US	S	NA	No	Power control

Register overview


Register	Offset	Description
TASKS_CONSTLAT	0x30	Enable Constant Latency mode
TASKS_LOWPWR	0x34	Enable Low-power mode (variable latency)
SUBSCRIBE_CONSTLAT	0xB0	Subscribe configuration for task CONSTLAT
SUBSCRIBE_LOWPWR	0xB4	Subscribe configuration for task LOWPWR
EVENTS_POFWARN	0x130	Power failure warning
EVENTS_SLEEPENTER	0x134	CPU entered WFI/WFE sleep
EVENTS_SLEEPEXIT	0x138	CPU exited WFI/WFE sleep
PUBLISH_SLEEPENTER	0x1B4	Publish configuration for event SLEEPENTER
PUBLISH_SLEEPEXIT	0x1B8	Publish configuration for event SLEEPEXIT
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
GPREGRET[n]	0x500	General purpose retention register This register is retained.
CONSTLATSTAT	0x520	Status of constant latency

TASKS_CONSTLAT

Address offset: 0x30

Enable Constant Latency mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_CONSTLAT										Enable Constant Latency mode
			Trigger	1								Trigger task

TASKS_LOWPWR

Address offset: 0x34

Enable Low-power mode (variable latency)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_LOWPWR										Enable Low-power mode (variable latency)
			Trigger	1								Trigger task

Address offset: 0xB0

Subscribe configuration for task CONSTLAT


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task CONSTLAT will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

Address offset: 0xB4

Subscribe configuration for task LOWPWR


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task LOWPWR will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

EVENTS_POFWARN

Address offset: 0x130

Power failure warning


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_POFWARN										Power failure warning
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_SLEEPENTER

Address offset: 0x134

CPU entered WFI/WFE sleep


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_SLEEPENTER										CPU entered WFI/WFE sleep
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_SLEEPEXIT

Address offset: 0x138

CPU exited WFI/WFE sleep


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_SLEEPEXIT										CPU exited WFI/WFE sleep
			NotGenerated	0								Event not generated
			Generated	1								Event generated

PUBLISH_SLEEPENTER

Address offset: 0x1B4

Publish configuration for event SLEEPENTER


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event SLEEPENTER will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_SLEEPEXIT

Address offset: 0x1B8

Publish configuration for event SLEEPEXIT


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event SLEEPEXIT will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																					C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	POFWARN										Enable or disable interrupt for event POFWARN
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	SLEEPENTER										Enable or disable interrupt for event SLEEPENTER
			Disabled	0								Disable
			Enabled	1								Enable
C	RW	SLEEPEXIT										Enable or disable interrupt for event SLEEPEXIT
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																					C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	POFWARN										Write '1' to enable interrupt for event POFWARN
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	SLEEPENTER										Write '1' to enable interrupt for event SLEEPENTER
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1S	SLEEPEXIT										Write '1' to enable interrupt for event SLEEPEXIT
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																					C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	POFWARN										Write '1' to disable interrupt for event POFWARN
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1C	SLEEPENTER										Write '1' to disable interrupt for event SLEEPENTER
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1C	SLEEPEXIT										Write '1' to disable interrupt for event SLEEPEXIT
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

GPREGRET[n]

Address offset: 0x500 + (n × 0x4)

General purpose retention register

This register is retained.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	GPREGRET										General purpose retention register This register is retained

CONSTLATSTAT

Address offset: 0x520

Status of constant latency


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	STATUS										Status
			Disable	0								Constant latency disabled
			Enable	1								Constant latency enabled