CRACEN — Cryptographic accelerator engine

The main features of the CRACEN peripheral are the following:

Cryptomaster – Symmetric cryptographic engines and digest engines
- AES
  - Supports 128-, 192-, and 256-bit keys
  - Masking countermeasures
  - Context switching
- HASH – including MD5, SHA1, SHA224, SHA256, SHA384, SHA512, and HMAC
- ChaChaPoly
- SHA3, SHAKE128, and SHAKE256
- SM4
Public Key cryptographic engine (PKE) and Isolated Key Generator (IKG)
- Modular exponentiation – RSA with and without CRT; 4096-bit maximum operand size
- Elliptic Curve Cryptography (ECC) with 640-bit maximum operand size
- Digital Signature Algorithm (DSA) and Elliptic Curve Digital Signature Algorithm (ECDSA, EC-KCDSA, and EdDSA), with 4096-bit maximum operand size
- Diffie-Hellman (D-H and ECDH) key exchange
Random Number Generator (RNG)

Figure 1. Cryptographic accelerator engine block diagram

Initialization

Before the CRACEN peripheral can be used, it must be configured.

At reset, each hardware crypto operation category is disabled and must be individually enabled using the ENABLE register. To use CRACEN, the desired module must first be enabled. Ongoing crypto operations will complete even if the module is disabled during the operation.

Before transferring data to CRACENCORE, CRACEN must be enabled using ENABLE.

When CRACEN is enabled, it will erase the PKE data RAM by starting a zeroization process. When the PKBUSY field of the PK.STATUS is cleared, the zeroization operation is complete. The PKE engine is not available until the zeroization process has finished.

Protected RAM

Protected RAM regions can be retained and locked for storing symmetric keys. The CPU cannot access these regions.

After KMU has pushed keys into the protected RAM, PROTECTEDRAMLOCK must be set to Enabled before CRACEN can access and use the keys.

The following areas are defined for the protected RAM.


Protected RAM
Address	End address	Description
0x51810040	0x5181005F	AES Protected key 0
0x51810060	0x5181007F	AES Protected key 1
0x51810080	0x5181008F	SM4 Protected key 0
0x51810090	0x5181009F	SM4 Protected key 1
0x518100A0	0x518100AF	SM4 Protected key 2
0x518100B0	0x518100BF	SM4 Protected key 3

Countermeasures

CRACEN contains security countermeasures to prevent malicious usage.

The following engines implement countermeasures:

AES – Masking against Simple Power Analysis (SPA) and Differential Power Analysis (DPA)
SM4 – Masking against SPA and DPA
IKG/PKE – Protection against timing attacks and DPA

If CRACEN IKG/PKE is used maliciously, a TAMPC event will be generated and countermeasures enacted according to the TAMPC configuration. The countermeasures are controlled by TAMPC. The bits in TAMPC that control the countermeasures have lock bits.

Isolated Key Generator

The Isolated Key Generator (IKG) is a module that derives symmetric and asymmetric keys from the unique seed and optional personalization string.

After IKG has been enabled, CRACEN performs an IKG health test. The CTRDRBGBUSY field of the IKG.STATUS is cleared when the operation has completed. IKG is started by writing to the IKG.START register. The generated IKG keys are valid as long as CRACEN remains enabled. For details on enabling and disabling CRACEN, see ENABLE.

The IKG derives the following keys from seed upon request:

One 256-bit ECC P-256 key
Two 256-bit AES keys

Note: The IKG generated keys are not directly accessible by CPU but are used by the PKE and AES engines. The IKG generated AES keys are not the same as protected keys in protected RAM, but can be used by the same AES engine.

Loading seed to IKG

The seed used by the IKG to generate keys must be pushed by the KMU to the SEED register and marked as valid before the keys can be generated.

To create and derive a seed the following sequence of operations are needed.

Create device unique seed:
1. Create 3 x 128 bit random number using CRACEN RNG
2. Provision random number to KMU slots, e.g. 0, 1, and 2 (128 bits in each slot)
  1. SRC.DEST = CRACEN.SEED[n], where n=0, 4, and 8.
  2. SRC.VALUE = random[i], where i=0,1, and 2 (i.e. random number results from CRACEN.RND operation above)
Load seed from KMU to CRACEN:
1. Push the KMU slots where the SEED is stored, e.g. KMU slots 0, 1, and 2
2. Write CRACEN.SEEDVALID register to mark the seed as valid for the IKG
3. To prevent any subsequent changes to the SEED, write CRACEN.SEEDLOCK register.

Note: Any IKG key generations without valid seed (CRACEN.SEEDVALID) will fail.

Low power

To ensure lowest possible power consumption when the peripheral is not needed, disable CRACEN.

Make sure any operations are finished before disabling the peripheral in register ENABLE.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
CRACEN	GLOBAL	0x50048000	HF	S	NSA	No	Crypto accelerator

Configuration


Instance	Domain	Configuration
CRACEN	GLOBAL	Access to CRACEN registers is blocked while KMU is performing a PUSH operation. CRACEN cannot write RRAM. CRACEN CRYPTOACCELERATOR specific configuration registers included PKE data (address 0x51808000) must be read and written using aligned access, i.e. using an operation where a word-aligned address is used for a word, or a halfword-aligned address is used for a halfword access. PKE code (address 0x5180C000) must be read and written using aligned access, i.e. using an operation where a word-aligned address is used for a word, or a halfword-aligned address is used for a halfword access.

Register overview


Register	Offset	Description
EVENTS_CRYPTOMASTER	0x100	Event indicating that interrupt triggered at Cryptomaster
EVENTS_RNG	0x104	Event indicating that interrupt triggered at RNG
EVENTS_PKEIKG	0x108	Event indicating that interrupt triggered at PKE or IKG
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
INTPEND	0x30C	Pending interrupts
ENABLE	0x400	Enable CRACEN peripheral modules.
SEEDVALID	0x404	Marks the SEED register as valid.
SEED[n]	0x410	Seed word [n] for symmetric and asymmetric key generation. This register is only writable from KMU.
SEEDLOCK	0x440	Lock the access to the SEED register.
PROTECTEDRAMLOCK	0x444	Lock the access to the protected RAM.

EVENTS_CRYPTOMASTER

Address offset: 0x100

Event indicating that interrupt triggered at Cryptomaster

The interrupt source must be cleared at Cryptomaaster before clearing this event.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_CRYPTOMASTER										Event indicating that interrupt triggered at Cryptomaster The interrupt source must be cleared at Cryptomaaster before clearing this event.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_RNG

Address offset: 0x104

Event indicating that interrupt triggered at RNG

The interrupt source must be cleared at RNG before clearing this event.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_RNG										Event indicating that interrupt triggered at RNG The interrupt source must be cleared at RNG before clearing this event.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_PKEIKG

Address offset: 0x108

Event indicating that interrupt triggered at PKE or IKG

The interrupt source must be cleared at PKE or IKG before clearing this event.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_PKEIKG										Event indicating that interrupt triggered at PKE or IKG The interrupt source must be cleared at PKE or IKG before clearing this event.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CRYPTOMASTER										Enable or disable interrupt for event CRYPTOMASTER The interrupt source must be cleared at Cryptomaaster before clearing this event.
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	RNG										Enable or disable interrupt for event RNG The interrupt source must be cleared at RNG before clearing this event.
			Disabled	0								Disable
			Enabled	1								Enable
C	RW	PKEIKG										Enable or disable interrupt for event PKEIKG The interrupt source must be cleared at PKE or IKG before clearing this event.
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	CRYPTOMASTER										Write '1' to enable interrupt for event CRYPTOMASTER The interrupt source must be cleared at Cryptomaaster before clearing this event.
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	RNG										Write '1' to enable interrupt for event RNG The interrupt source must be cleared at RNG before clearing this event.
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1S	PKEIKG										Write '1' to enable interrupt for event PKEIKG The interrupt source must be cleared at PKE or IKG before clearing this event.
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	CRYPTOMASTER										Write '1' to disable interrupt for event CRYPTOMASTER The interrupt source must be cleared at Cryptomaaster before clearing this event.
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1C	RNG										Write '1' to disable interrupt for event RNG The interrupt source must be cleared at RNG before clearing this event.
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1C	PKEIKG										Write '1' to disable interrupt for event PKEIKG The interrupt source must be cleared at PKE or IKG before clearing this event.
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTPEND

Address offset: 0x30C

Pending interrupts


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CRYPTOMASTER										Read pending status of interrupt for event CRYPTOMASTER The interrupt source must be cleared at Cryptomaaster before clearing this event.
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
B	R	RNG										Read pending status of interrupt for event RNG The interrupt source must be cleared at RNG before clearing this event.
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
C	R	PKEIKG										Read pending status of interrupt for event PKEIKG The interrupt source must be cleared at PKE or IKG before clearing this event.
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending

ENABLE

Address offset: 0x400

Enable CRACEN peripheral modules.

Each module of CRACEN can be enabled individually. When any of these modules are not in use, it can be disabled to save power. The module you want to use must first be enabled. Any ongoing crypto operations will be finished even if the module is disabled during the operation.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CRYPTOMASTER										Enable cryptomaster
			Disabled	0								Cryptomaster disabled.
			Enabled	1								Cryptomaster enabled.
B	RW	RNG										Enable RNG
			Disabled	0								RNG disabled.
			Enabled	1								RNG enabled.
C	RW	PKEIKG										Enable PKE and IKG
			Disabled	0								PKE and IKG disabled.
			Enabled	1								PKE and IKG enabled.

SEEDVALID

Address offset: 0x404

Marks the SEED register as valid.

This register must be written after the SEED register is written, and before the IKG is started.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALID										Marks the SEED as valid
			Disabled	0								Valid disabled.
			Enabled	1								Valid enabled.

SEED[n]

Address offset: 0x410 + (n × 0x4)

Seed word [n] for symmetric and asymmetric key generation.

This register is only writable from KMU.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	VAL										Seed value

SEEDLOCK

Address offset: 0x440

Lock the access to the SEED register.

Note. If SEEDVALID was not written prior to SEEDLOCK, the write to SEEDLOCK will also mark the SEED as valid.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable the lock Only possible to write a value 1.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.

PROTECTEDRAMLOCK

Address offset: 0x444

Lock the access to the protected RAM.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable the lock Only possible to write a value 1.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
CRACENCORE	GLOBAL	0x51800000	HF	S	NSA	No	CRACEN core

Configuration


Instance	Domain	Configuration
CRACENCORE	GLOBAL	CRYPTMSTRDMA registers included CRYPTMSTRHW registers included RNGCONTROL registers included PK registers included IKG registers included RNGDATA registers included PKDATAMEMORY registers included PKUCODE registers included Using CRACENCORE configuration reset values

Register overview


Register	Offset	Description
CRYPTMSTRDMA.FETCHADDRLSB	0x000	Fetch Address Least Significant Word
CRYPTMSTRDMA.FETCHADDRMSB	0x004	Fetch Address Most Significant Word
CRYPTMSTRDMA.FETCHLEN	0x008	Fetch DMA Length (only used in direct mode)
CRYPTMSTRDMA.FETCHTAG	0x00C	Fetch User Tag (only used in direct mode)
CRYPTMSTRDMA.PUSHADDRLSB	0x010	Push Address Least Significant Word
CRYPTMSTRDMA.PUSHADDRMSB	0x014	Push Address Most Significant Word
CRYPTMSTRDMA.PUSHLEN	0x018	Push Length (only used in direct mode)
CRYPTMSTRDMA.INTEN	0x01C	Interrupt Enable mask
CRYPTMSTRDMA.INTENSET	0x020	Interrupt Set
CRYPTMSTRDMA.INTENCLR	0x024	Interrupt Clear
CRYPTMSTRDMA.INTSTATRAW	0x028	Interrupt Status Raw
CRYPTMSTRDMA.INTSTAT	0x02C	Interrupt Status
CRYPTMSTRDMA.INTSTATCLR	0x030	Interrupt Status Clear
CRYPTMSTRDMA.CONFIG	0x034	Cryptomaster configuration
CRYPTMSTRDMA.START	0x038	Start
CRYPTMSTRDMA.STATUS	0x03C	Status
CRYPTMSTRHW.INCLIPSHWCFG	0x400	Incuded IPs Hardware configuration
CRYPTMSTRHW.BA411EAESHWCFG1	0x404	Generic g_AesModesPoss value.
CRYPTMSTRHW.BA411EAESHWCFG2	0x408	Generic g_CtrSize value.
CRYPTMSTRHW.BA413HASHHWCFG	0x40C	Generic g_Hash value
CRYPTMSTRHW.BA418SHA3HWCFG	0x410	Generic g_Sha3CtxtEn value.
CRYPTMSTRHW.BA419SM4HWCFG	0x414	Generic g_SM4ModesPoss value.
CRYPTMSTRHW.BA424ARIAHWCFG	0x418	Generic g_aria_modePoss value.
RNGCONTROL.CONTROL	0x1000	Control register
RNGCONTROL.FIFOLEVEL	0x1004	FIFO level register.
RNGCONTROL.FIFOTHRESHOLD	0x1008	FIFO threshold register.
RNGCONTROL.FIFODEPTH	0x100C	FIFO depth register.
RNGCONTROL.KEY[n]	0x1010	Key register.
RNGCONTROL.TESTDATA	0x1020	Test data register.
RNGCONTROL.REPEATTHRESHOLD	0x1024	Repetition Test Count Cut-Off value.
RNGCONTROL.PROPTHRESHOLD	0x1028	Adaptive Proportion Test (1024-sample window) Cut-Off value.
RNGCONTROL.STATUS	0x1030	Status register.
RNGCONTROL.INITWAITVAL	0x1034	Initial wait counter value.
RNGCONTROL.DISABLEOSC[n]	0x1038	Disable oscillator rings #n32 to #((n+1)32)-1.
RNGCONTROL.SWOFFTMRVAL	0x1040	Switch off timer value.
RNGCONTROL.CLKDIV	0x1044	Sample clock divider.
RNGCONTROL.AIS31CONF0	0x1048	AIS31 configuration register 0.
RNGCONTROL.AIS31CONF1	0x104C	AIS31 configuration register 1.
RNGCONTROL.AIS31CONF2	0x1050	AIS31 configuration register 2.
RNGCONTROL.AIS31STATUS	0x1054	AIS31 status register.
RNGCONTROL.HWCONFIG	0x1058	Hardware configuration register.
RNGCONTROL.FIFO[n]	0x1080	FIFO data
PK.POINTERS	0x2000	Pointers register.
PK.COMMAND	0x2004	Command register.
PK.CONTROL	0x2008	Command register.
PK.STATUS	0x200C	Status register.
PK.TIMER	0x2014	Timer register.
PK.HWCONFIG	0x2018	Hardware configuration register.
PK.OPSIZE	0x201C	Operand size register.
PK.RAMERRORINJECT	0x2040	RAM error injection register.
PK.RAMERRORSTATUS	0x2044	RAM error status register.
IKG.START	0x3000	Start register.
IKG.STATUS	0x3004	Status register.
IKG.INITDATA	0x3008	InitData register.
IKG.NONCE	0x300C	Nonce register.
IKG.PERSONALISATIONSTRING	0x3010	Personalisation String register.
IKG.RESEEDINTERVALLSB	0x3014	Reseed Interval LSB register.
IKG.RESEEDINTERVALMSB	0x3018	Reseed Interval MSB register.
IKG.PKECONTROL	0x301C	PKE Control register.
IKG.PKECOMMAND	0x3020	PKE Command register.
IKG.PKESTATUS	0x3024	PKE Status register.
IKG.SOFTRST	0x3028	SoftRst register.
IKG.HWCONFIG	0x302C	HwConfig register.

CRYPTMSTRDMA.FETCHADDRLSB

Address offset: 0x000

Fetch Address Least Significant Word


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHADDRLSB										Address In direct mode this register is written by SW with the address of the data block. In Scatter-gather mode this register is written by SW with the address of the first descriptor, and subsequently updated by the hardware after each processed descriptor.

CRYPTMSTRDMA.FETCHADDRMSB

Address offset: 0x004

Fetch Address Most Significant Word


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHADDRMSB										As the platform has 32bit addresses this register and ADDRMSB registers both give access to the same 32-bit register.

CRYPTMSTRDMA.FETCHLEN

Address offset: 0x008

Fetch DMA Length (only used in direct mode)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID						C	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHLEN										Length of data block
B	RW	FETCHCSTADDR										Constant address
C	RW	FETCHREALIGN										Realign length

CRYPTMSTRDMA.FETCHTAG

Address offset: 0x00C

Fetch User Tag (only used in direct mode)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHTAG										User tag

CRYPTMSTRDMA.PUSHADDRLSB

Address offset: 0x010

Push Address Least Significant Word


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PUSHADDRLSB										Address In direct mode this register is written by SW with the address of the data block. In Scatter-gather mode this register is written by SW with the address of the first descriptor, and subsequently updated by the hardware after each processed descriptor.

CRYPTMSTRDMA.PUSHADDRMSB

Address offset: 0x014

Push Address Most Significant Word


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PUSHADDRMSB										As the platform has 32bit addresses this register and ADDRMSB registers both give access to the same 32-bit register.

CRYPTMSTRDMA.PUSHLEN

Address offset: 0x018

Push Length (only used in direct mode)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					D	C	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PUSHLEN										Length of data block
B	RW	PUSHCSTADDR										Constant address
C	RW	PUSHREALIGN										Realign length
D	RW	PUSHDISCARD										Discard data

CRYPTMSTRDMA.INTEN

Address offset: 0x01C

Interrupt Enable mask


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHERBLOCKEND										Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
B	RW	FETCHERSTOPPED										Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer
C	RW	FETCHERERROR										Bus error during fetcher DMA access
D	RW	PUSHERBLOCKEND										Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
E	RW	PUSHERSTOPPED										Pusher DMA reached the end of a block with Stop=1, or end of direct transfer
F	RW	PUSHERERROR										Bus error during pusher DMA access

CRYPTMSTRDMA.INTENSET

Address offset: 0x020

Interrupt Set

Writing a 1 to a bit in this register enables the corresponding interrupt. Writing 0 has no effect.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHERBLOCKEND										Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
B	RW	FETCHERSTOPPED										Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer
C	RW	FETCHERERROR										Bus error during fetcher DMA access
D	RW	PUSHERBLOCKEND										Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
E	RW	PUSHERSTOPPED										Pusher DMA reached the end of a block with Stop=1, or end of direct transfer
F	RW	PUSHERERROR										Bus error during pusher DMA access

CRYPTMSTRDMA.INTENCLR

Address offset: 0x024

Interrupt Clear

Writing a 1 to a bit in this register disables the corresponding interrupt. Writing 0 has no effect.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHERBLOCKEND										Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
B	RW	FETCHERSTOPPED										Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer
C	RW	FETCHERERROR										Bus error during fetcher DMA access
D	RW	PUSHERBLOCKEND										Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
E	RW	PUSHERSTOPPED										Pusher DMA reached the end of a block with Stop=1, or end of direct transfer
F	RW	PUSHERERROR										Bus error during pusher DMA access

CRYPTMSTRDMA.INTSTATRAW

Address offset: 0x028

Interrupt Status Raw

Interrupt status before bitmasking with INTEN.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHERBLOCKEND										Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
B	RW	FETCHERSTOPPED										Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer
C	RW	FETCHERERROR										Bus error during fetcher DMA access
D	RW	PUSHERBLOCKEND										Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
E	RW	PUSHERSTOPPED										Pusher DMA reached the end of a block with Stop=1, or end of direct transfer
F	RW	PUSHERERROR										Bus error during pusher DMA access

CRYPTMSTRDMA.INTSTAT

Address offset: 0x02C

Interrupt Status

Interrupt Status after bitmasking with INTEN. If any bit of this register is high, this sub-module interrupt line towards the CRACEN interrupt generation logic is high.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHERBLOCKEND										Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
B	RW	FETCHERSTOPPED										Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer
C	RW	FETCHERERROR										Bus error during fetcher DMA access
D	RW	PUSHERBLOCKEND										Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
E	RW	PUSHERSTOPPED										Pusher DMA reached the end of a block with Stop=1, or end of direct transfer
F	RW	PUSHERERROR										Bus error during pusher DMA access

CRYPTMSTRDMA.INTSTATCLR

Address offset: 0x030

Interrupt Status Clear

Writing a 1 to a bit in this register clears the corresponding interrupt. Writing 0 has no effect.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHERBLOCKEND										Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
B	RW	FETCHERSTOPPED										Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer
C	RW	FETCHERERROR										Bus error during fetcher DMA access
D	RW	PUSHERBLOCKEND										Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only)
E	RW	PUSHERSTOPPED										Pusher DMA reached the end of a block with Stop=1, or end of direct transfer
F	RW	PUSHERERROR										Bus error during pusher DMA access

CRYPTMSTRDMA.CONFIG

Address offset: 0x034

Cryptomaster configuration


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FETCHCTRLINDIRECT										Fetcher scatter/gather. When this bit is zero, the fetcher runs in direct mode. When this bit is one, the fetcher runs in scatter-gather mode.
B	RW	PUSHCTRLINDIRECT										Pusher scatter/gather. When this bit is zero, the pusher runs in direct mode. When this bit is one, the pusher runs in scatter-gather mode.
C	RW	FETCHSTOP										Stop fetcher. When this bit is high, the fetcher will stop at the end of the current block (even if the STOP bit in the descriptor is low).
D	RW	PUSHSTOP										Stop pusher DMA. When this bit is high, the pusher will stop at the end of the current block (even if the STOP bit in the descriptor is low).
E	RW	SOFTRST										Soft reset the cryptomaster. When this bit is high, the software reset of the DMA modules, the FIFO's and the processing module will be activated. The bus is not affected (pending transfers will be completed).

CRYPTMSTRDMA.START

Address offset: 0x038

Start


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	STARTFETCH										Writing a '1' starts the fetcher DMA. Writing a '0' has no effect.
B	W	STARTPUSH										Writing a '1' starts the pusher DMA. Writing a '0' has no effect.

CRYPTMSTRDMA.STATUS

Address offset: 0x03C

Status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				F	F	F	F	F	F	F	F	F	F	F	F	F	F	F	F										E	D	C			B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	FETCHBUSY										This bit is high as long as the fetcher DMA is busy.
B	R	PUSHBUSY										This bit is high as long as the pusher DMA is busy.
C	R	FETCHNOTEMPTY										Not empty flag for fetcher DMA input FIFO
D	R	PUSHWAITINGFIFO										Pusher DMA Waiting FIFO. This bit is high when the pusher is waiting for more data in output FIFO.
E	R	SOFTRSTBUSY										This bit is high when the soft reset is on going
F	R	PUSHNBDATA										Amount of data in the pusher DMA output FIFO

CRYPTMSTRHW.INCLIPSHWCFG

Address offset: 0x400

Incuded IPs Hardware configuration


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																						N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000771				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1	1	1	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	R	BA411AESINCLUDED										Generic g_IncludeAES value. BA411E–AES IP included if set
B	R	BA415HPAESGCMINCLUDED										Generic g_IncludeAESGCM value. BA415–HP-AES-GCM IP included if set
C	R	BA416HPAESXTSINCLUDED										Generic g_IncludeAESXTS value. BA416–HP-AES-XTS IP included if set
D	R	BA412DESINCLUDED										Generic g_IncludeDES value. BA412–3DES IP included if set
E	R	BA413HASHINCLUDED										Generic g_IncludeHASH value. BA413–HASH IP included if set
F	R	BA417CHACHAPOLYINCLUDED										Generic g_IncludeChachaPoly value. BA417–ChaChaPoly IP included if set
G	R	BA418SHA3INCLUDED										Generic g_IncludeSHA3 value. BA418–SHA3 IP included if set
H	R	BA421ZUCINCLUDED										Generic g_IncludeZUC value. BA421–ZUC IP included if set
I	R	BA419SM4INCLUDED										Generic g_IncludeSM4 value. BA419–SM4 IP included if set
J	R	BA414EPPKEINCLUDED										Generic g_IncludePKE value. BA414EP-PKE IP included if set
K	R	BA431NDRNGINCLUDED										Generic g_IncludeNDRNG value. BA431–NDRNG IP included if set
L	R	BA420HPCHACHAPOLYINCLUDED										Generic g_IncludeHPChachaPoly value. BA420–HP-ChaChaPoly IP included if set
M	R	BA423SNOW3GINCLUDED										Generic g_IncludeSnow3G value. BA423–Snow3G IP included if set
N	R	BA422KASUMIINCLUDED										Generic g_IncludeKasumi value. BA422–Kasumi IP included if set

CRYPTMSTRHW.BA411EAESHWCFG1

Address offset: 0x404

Generic g_AesModesPoss value.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID									D	D	D							C	B								A	A	A	A	A	A	A	A	A
Reset 0x070301FF				0	0	0	0	0	1	1	1	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	BA411EAESHWCFGMODE										Generic g_AesModesPoss value. BA411E-AES engine configuration.
B	R	BA411EAESHWCFGCS										Generic g_CS value. BA411E-AES engine configuration.
C	R	BA411EAESHWCFGMASKING										Generic g_UseMasking value. BA411E-AES engine configuration.
D	R	BA411EAESHWCFGKEYSIZE										Generic g_Keysize value. BA411E-AES engine configuration.

CRYPTMSTRHW.BA411EAESHWCFG2

Address offset: 0x408

Generic g_CtrSize value.

BA411E-AES engine configuration.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000080				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	BA411EAESHWCFG2										Generic g_CtrSize value. BA411E-AES engine configuration.

CRYPTMSTRHW.BA413HASHHWCFG

Address offset: 0x40C

Generic g_Hash value


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																	D	C	B										A	A	A	A	A	A	A
Reset 0x0003003F				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	BA413HASHHWCFGMASK										Generic g_HashMaskFunc value. BA413-Hash engine configuration.
B	R	BA413HASHHWCFGPADDING										Generic g_HashPadding value. BA413-Hash engine configuration.
C	R	BA413HASHHWCFGHMAC										Generic g_HMAC_enabled value. BA413-Hash engine configuration.
D	R	BA413HASHHWCFGVERIFYDIGEST										Generic g_HashVerifyDigest value. BA413-Hash engine configuration.

CRYPTMSTRHW.BA418SHA3HWCFG

Address offset: 0x410

Generic g_Sha3CtxtEn value.

BA418-SHA3 configuration.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	R	BA418SHA3HWCFG										Generic g_Sha3CtxtEn value. BA418-SHA3 configuration.

CRYPTMSTRHW.BA419SM4HWCFG

Address offset: 0x414

Generic g_SM4ModesPoss value.

BA419-SM4 engine configuration.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																		B								A	A	A	A	A	A	A	A	A	A
Reset 0x000201FF				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	BA419SM4HWCFG										Generic g_SM4ModesPoss value. BA419-SM4 engine configuration.
B	R	USEMASKING										Generic g_sm4UseMasking value. BA419-SM4 engine configuration.

CRYPTMSTRHW.BA424ARIAHWCFG

Address offset: 0x418

Generic g_aria_modePoss value.

BA424-Aria engine configuration.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																											A	A	A	A	A	A	A	A	A
Reset 0x0000017F				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	BA424ARIAHWCFG										Generic g_aria_modePoss value. BA424-Aria engine configuration.

RNGCONTROL.CONTROL

Address offset: 0x1000

Control register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID															Q	P	P	P	P	O	N	M	L	K	J	I	H	G		F	E	D	C	B	A
Reset 0x00040000				0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable the RNG. Clearing this bit resets the RNG FSM.
B	RW	LFSREN										Select between the RNG with asynchronous free running ring oscillators (when 0) and the Pseudo-Random generator with synchronous oscillators for simulation purpose (when 1).
C	RW	TESTEN										Select input for conditioning function and continuous tests:
			NORMAL	0								Noise source (normal mode).
			TEST	1								Test data register (test mode).
D	RW	CONDBYPASS										Conditioning function bypass.
			NORMAL	0								the conditioning function is used (normal mode).
			BYPASS	1								the conditioning function is bypassed (to observe entropy source directly).
E	RW	INTENREP										Interrupt enable for Repetition Count Test failure.
F	RW	INTENPROP										Interrupt enable for Adaptive Proportion Test failure (1024-sample window).
G	RW	INTENFULL										Interrupt enable for FIFO full.
H	RW	SOFTRST										Software reset: This bit is not cleared automatically.
			NORMAL	0								Normal mode.
			CTEST	1								The continuous test, the conditioning function and the FIFO are reset.
I	RW	INTENPRE										Interrupt enable for AIS31 preliminary noise alarm.
J	RW	INTENALM										Interrupt enable for AIS31 noise alarm.
K	RW	FORCEACTIVEROS										Force oscillators to run when FIFO is full.
L	RW	HEALTHTESTBYPASS										Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state.
M	RW	AIS31BYPASS										Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state.
N	RW	HEALTHTESTSEL										Select input to health test module:
			BEFORE	0								Before conditioning.
			AFTER	1								After conditioning.
O	RW	AIS31TESTSEL										Select input to the AIS31 test module:
			BEFORE	0								Before conditioning.
			AFTER	1								After conditioning.
P	RW	NB128BITBLOCKS										Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.
Q	RW	FIFOWRITESTARTUP										Enable write of the samples in the FIFO during start-up.

RNGCONTROL.FIFOLEVEL

Address offset: 0x1004

FIFO level register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW RME	FIFOLEVEL										Number of 32 bits words of random values available in the FIFO. Any read to this register clears the FULLINT flag in the STATUS register, but does not affect this register content. Note that if the FIFO is still full, the status flag and interrupt will be set back up right away

RNGCONTROL.FIFOTHRESHOLD

Address offset: 0x1008

FIFO threshold register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000003				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	FIFOTHRESHOLD										FIFO level threshold below which the module leaves the idle state to refill the FIFO. Expressed in number of 128bit blocks. After a FIFO read, the RNG will start refilling the FIFO if FIFOLEVEL is smaller than (FIFOTHRESHOLD + 1) * 4

RNGCONTROL.FIFODEPTH

Address offset: 0x100C

FIFO depth register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	FIFODEPTH										Maximum number of 32 bits words that can be stored in the FIFO: 2**g_fifodepth.

RNGCONTROL.KEY[n]

Address offset: 0x1010 + (n × 0x4)

Key register.

128-bit AES key used for conditioning


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	KEY										Key register. Note: Byte 0 of Key0 is the MSB and byte 3 of Key3 is the LSB.

RNGCONTROL.TESTDATA

Address offset: 0x1020

Test data register.

This register is used to feed known data to the conditioning function or to the continuous tests. When one word is written into this register, the 32-bit are sent to those modules. Since some time is needed for processing, there is one busy flag (TESTDATABUSY in the STATUS register) going high as soon as data is written, and going low when the next word can be written. Write access to this register is ignored when CONTROL.TESTEN is 0. Test data written through this interface is expected to be a multiple of 128 bits.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TESTDATA										Test data register.

RNGCONTROL.REPEATTHRESHOLD

Address offset: 0x1024

Repetition Test Count Cut-Off value.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														A	A	A	A	A	A
Reset 0x00000029				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	REPEATTHRESHOLD										Repetition Test Count Cut-Off value.

RNGCONTROL.PROPTHRESHOLD

Address offset: 0x1028

Adaptive Proportion Test (1024-sample window) Cut-Off value.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										A	A	A	A	A	A	A	A	A	A
Reset 0x00000319				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PROPTHRESHOLD										Adaptive Proportion Test (1024-sample window) Cut-Off value.

RNGCONTROL.STATUS

Address offset: 0x1030

Status register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																								I	H	G	F	E		D	C	B	B	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	TESTDATABUSY										High when data written to TestData register is being processed.
B	R	STATE										State of the control FSM:
			RESET	0								Reset
			STARTUP	1								Startup
			IDLERON	2								Idle (Rings On)
			IDLEROFF	3								Idle (Rings Off)
			FILLFIFO	4								Fill FIFO
			ERROR	5								Error
C	RW	REPFAIL										NIST-800-90B repetition Count Test interrupt status.
D	RW	PROPFAIL										NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status.
E	RW	FULLINT										FIFO full status.
F	RW	PREINT										AIS31 preliminary noise alarm interrupt status.
G	RW	ALMINT										AIS31 noise alarm interrupt status.
H	R	STARTUPFAIL										Start-up test failure.
I	RW	FIFOACCFAIL										Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0).

RNGCONTROL.INITWAITVAL

Address offset: 0x1034

Initial wait counter value.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x0000FFFF				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	INITWAITVAL										Number of clock cycles to wait before sampling data from the noise source.

RNGCONTROL.DISABLEOSC[n]

Address offset: 0x1038 + (n × 0x4)

Disable oscillator rings #n*32 to #((n+1)*32)-1.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DISABLEOSC										Disable oscillator rings #n32 to #((n+1)32)-1.

RNGCONTROL.SWOFFTMRVAL

Address offset: 0x1040

Switch off timer value.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x0000FFFF				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	SWOFFTMRVAL										Number of clk cycles to wait before stopping the rings after the FIFO is full.

RNGCONTROL.CLKDIV

Address offset: 0x1044

Sample clock divider.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CLKDIV										Sample clock divider. The frequency at which the outputs of the rings are sampled is given by: Fs=Fpclk/(ClkDiv+1).

RNGCONTROL.AIS31CONF0

Address offset: 0x1048

AIS31 configuration register 0.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					B	B	B	B	B	B	B	B	B	B	B	B	B	B	B		A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x43401040				0	1	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	STARTUPTHRESHOLD										Start-up test threshold.
B	RW	ONLINETHRESHOLD										Online threshold.

RNGCONTROL.AIS31CONF1

Address offset: 0x104C

AIS31 configuration register 1.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					B	B	B	B	B	B	B	B	B	B	B	B	B	B	B		A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x03C00680				0	0	0	0	0	0	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ONLINEREPTHRESHOLD										Online repeat threshold.
B	RW	HEXPECTEDVALUE										Expected history value.

RNGCONTROL.AIS31CONF2

Address offset: 0x1050

AIS31 configuration register 2.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					B	B	B	B	B	B	B	B	B	B	B	B	B	B	B		A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x04400340				0	0	0	0	0	1	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	HMIN										Minimum allowed history value.
B	RW	HMAX										Maximum allowed history value.

RNGCONTROL.AIS31STATUS

Address offset: 0x1054

AIS31 status register.

This register is used to obtain diagnostic information about the AIS31 start-up and online tests. Writing to this register clears the NUMPRELIMALARMS value. The PRELIMNOISEALARMREP and PRELIMNOISEALARMRNG flags are cleared by clearing the PREINT flag in the STATUS register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																		C	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	NUMPRELIMALARMS										Number of preliminary noise alarms since counter was last cleared.
B	RW	PRELIMNOISEALARMRNG										Last preliminary noise alarm occurred due to history value out of range.
C	RW	PRELIMNOISEALARMREP										Last preliminary noise alarm occurred due to consecutive high Χ**2.

RNGCONTROL.HWCONFIG

Address offset: 0x1058

Hardware configuration register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										C	B	A	A	A	A	A	A	A	A
Reset 0x00000337				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	1	1	0	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	NUMBOFRINGS										Generic g_NumRings value.
B	R	AIS31										Generic g_AIS31 value.
C	R	AIS31FULL										Generic g_AIS31Full value.

RNGCONTROL.FIFO[n]

Address offset: 0x1080 + (n × 0x4)

FIFO data

The FIFO contains the RNG output data.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATA										FIFO data

PK.POINTERS

Address offset: 0x2000

Pointers register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID								D	D	D	D					C	C	C	C					B	B	B	B					A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	OPPTRA										When executing primitive arithmetic operations, this pointer defines where operand A is located in memory (location 0x0 to 0xF).
B	RW	OPPTRB										When executing primitive arithmetic operations, this pointer defines where operand B is located in memory (location 0x0 to 0xF).
C	RW	OPPTRC										When executing primitive arithmetic operations, this pointer defines the location (0x0 to 0xF) where the result will be stored in memory.
D	RW	OPPTRN										When executing primitive arithmetic operations, this pointer defines the location where the modulus is located in memory (location 0x0 to 0xF).

PK.COMMAND

Address offset: 0x2004

Command register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				L	K	J	I		H	G	F		E	E	E	D		C	C	C	C	C	C	C	C	C	C	B	A	A	A	A	A	A	A
Reset 0x0000000F				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	OPEADDR										This field defines the operation to be performed. See documentation for more details.
B	RW	FIELDF										0: Field is GF(p) 1: Field is GF(2**m)
C	RW	OPBYTESM1										This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: - 0x014 - ECC on curve K-163 - 0x01F - ECC on curve P-256 - 0x02F - ECC on curve P-384 - 0x033 - ECC on curve K-409 - 0x041 - ECC on curve P-521 - 0x07F - 1024-bit RSA - 0x09F - 1280-bit RSA - 0x1FF - 4096-bit RSA - 0x3FF - 8192-bit RSA
D	RW	RANDMOD										Enable randomization of modulus (counter-measure).
E	RW	SELCURVE										Enable accelerator for specific curve modulus: This field has no effect when the optional acceleration hardware is not included.
			NOACCEL	0x0								No acceleration (default)
			P256	0x1								P256
			P384	0x2								P384
			P521	0x3								P521
			P192	0x4								P192
			CURVE25519	0x5								Curve25519
			ED25519	0x6								Ed25519.
F	RW	RANDKE										Enable randomization of exponent/scalar (counter-measure).
G	RW	RANDPROJ										Enable randomization of projective coordinates (counter-measure).
H	RW	EDWARDS										Enable Edwards curve.
I	RW	SWAPBYTES										Swap the bytes on AHB interface: This bit must be programmed before writing/reading any data in data memory.
			NATIVE	0								Native format (little endian).
			SWAPPED	1								Byte swapped (big endian).
J	RW	FLAGA										Flag A.
K	RW	FLAGB										Flag B.
L	RW	CALCR2										This bit indicates if the IP has to calculate R**2 mod N for the next operation. This bit must be set to 1 when a new prime number has been programmed. This bit is used for primitive operations and ignored for the other operations.
			NRECALCULATE	0								don't recalculate R² mod N
			RECALCULATE	1								re-calculate R² mod N

PK.CONTROL

Address offset: 0x2008

Command register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	START										Writing a 1 starts the processing.
B	W	CLEARIRQ										Writing a 1 clears the IRQ output.

PK.STATUS

Address offset: 0x200C

Status register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID							D	D	D	D	D							C	B	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ERRORFLAGS										These bits indicate an error condition. They are updated at the end of the operation. They are cleared when starting a new operation.
B	R	PKBUSY										This bit reflects the BUSY output value. It is set when the operation starts and it is cleared when the operation is finished.
C	R	INTRPTSTATUS										This bit reflects the IRQ output value. It is set when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.
D	R	FAILPTR										These bits indicate which data location generated the error flag. They are not available for all error flags.

PK.TIMER

Address offset: 0x2014

Timer register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TIMER										Number of core clock cycles.

PK.HWCONFIG

Address offset: 0x2018

Hardware configuration register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				N	M	L				K	J	I	H	G	F		E	D	C	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x01F72200				0	0	0	0	0	0	0	1	1	1	1	1	0	1	1	1	0	0	1	0	0	0	1	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MAXOPSIZE										Maximum operand size (number of bytes).
B	R	NBMULT										Number of multipliers:
			MULT1	0								1 multiplier
			MULT4	1								4 multipliers
			MULT16	2								16 multipliers
			MULT64	4								64 multipliers
			MULT256	8								256 multipliers
C	R	PRIMEFIELD										Support prime field.
D	R	BINARYFIELD										Support binary field.
E	R	ECC										Support error correction.
F	R	P256										Support ECC P256 acceleration.
G	R	P384										Support ECC P384 acceleration.
H	R	P521										Support ECC P521 acceleration.
I	R	P192										Support ECC P192 acceleration.
J	R	X25519										Support Curve25519/Ed25519 acceleration.
K	R	AHBMASTER										Memory access
			SLAVE	0								Memory access through AHB Slave and internally in the PKE.
			MASTER	1								Memory access through AHB Master, outside the PKE.
L	R	DISABLESMX										State of DisableSMx input (high when SM2/SM9 operations are disabled).
M	R	DISABLECLRMEM										State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled).
N	R	DISABLECM										State of DisableCM input (high when counter-measures are disabled).

PK.OPSIZE

Address offset: 0x201C

Operand size register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																							A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00001000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	OPSIZE										Operand size (number of bytes): This register is used when the memory is accessed via AHB Master
			OPSIZE256	0x0100								256 bytes.
			OPSIZE521	0x0209								521 bytes.
			OPSIZE2048	0x0800								2048 bytes.
			OPSIZE3072	0x0C00								3072 bytes.
			OPSIZE4096	0x1000								4096 bytes.

PK.RAMERRORINJECT

Address offset: 0x2040

RAM error injection register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID										B	B	B	B	B	B	B	B	B	B							A	A	A	A	A	A	A	A	A	A
Reset 0x03FF03FF				0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	BITERROR1										Bit position of first error
B	RW	BITERROR2										Bit position of second error

PK.RAMERRORSTATUS

Address offset: 0x2044

RAM error status register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	RAMCORRECTION										This bit indicates that a 1-bit error has been detected and corrected on RAM interface
B	R	RAMFAILURE										This bit indicates that an uncorrectable error has been detected on the data RAM interface

IKG.START

Address offset: 0x3000

Start register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	START										Start the Isolated Key Generation.

IKG.STATUS

Address offset: 0x3004

Status register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												G	F	E	D		C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	SEEDERROR										Seed Error during Isolated Key Generation. When the IKG module is in error state, a reset is required to restart the module.
B	R	ENTROPYERROR										Entropy Error during Isolated Key Generation. When the IKG module is in error state, a reset is required to restart the module.
C	R	OKAY										Isolated Key Generation is okay.
D	R	CTRDRBGBUSY										CTR_DRBG health test is busy (only when g_hw_health_test = true).
E	R	CATASTROPHICERROR										Catastrophic error during CTR_DRBG health test (only when g_hw_health_test = true). When the IKG module is in error state, a reset is required to restart the module.
F	R	SYMKEYSTORED										Symmetric Keys are stored.
G	R	PRIVKEYSTORED										Private Keys are stored.

IKG.INITDATA

Address offset: 0x3008

InitData register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	INITDATA										Writing a 1 initialise Nonce and Personalisation_String registers counters, i.e. start writing from the 32 LSB.

IKG.NONCE

Address offset: 0x300C

Nonce register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	NONCE										Nonce (write/read value 32-bit by 32-bit).

IKG.PERSONALISATIONSTRING

Address offset: 0x3010

Personalisation String register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PERSONALISATIONSTRING										Personalisation String (write/read value 32-bit by 32-bit). If this register is not accessed, then Personalisation String is considered null.

IKG.RESEEDINTERVALLSB

Address offset: 0x3014

Reseed Interval LSB register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x80000000				1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESEEDINTERVALLSB										Reseed Interval LSB.

IKG.RESEEDINTERVALMSB

Address offset: 0x3018

Reseed Interval MSB register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESEEDINTERVALMSB										Reseed Interval MSB.

IKG.PKECONTROL

Address offset: 0x301C

PKE Control register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	PKESTART										Start the PKE operation or trigger for Secure mode exit.
B	W	CLEARIRQ										Clear the IRQ output.

IKG.PKECOMMAND

Address offset: 0x3020

PKE Command register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										C	C	B	B	B	B				A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	SECUREMODE										Secure mode. It is activated as soon as it is set to 1.It is deactivated when it is set to 0 and PKE_Start is set to 1.
			DEACTIVATED	0
			ACTIVATED	1
B	RW	SELECTEDKEY										Select Generated Private Key for PKE operation. This Key Index should be between 0 and g_nb_priv_keys-1.
C	RW	OPSEL										Select PKE operation with Isolated Key Note: Value 3 is reserved.
			PUBKEY	0								Public Key Generation
			ECDSA	1								ECDSA Signature
			PTMUL	2								Point Multiplication

IKG.PKESTATUS

Address offset: 0x3024

PKE Status register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																	E	D	C															B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ERROR										Error because either Private Keys are not stored or the operation is not defined.
B	R	STARTERROR										Error because a new operation is started while the previous one is still busy.
C	R	IKGPKBUSY										Busy, set when the operation starts and cleared when the operation is finished.
D	R	IRQSTATUS										IRQ, set when the operation is finished and cleared when the CPU writes the bit 1 of PKE_Control Register or a new operation is started.
E	R	ERASEBUSY										The PKE Data RAM is being erased.

IKG.SOFTRST

Address offset: 0x3028

SoftRst register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	SOFTRST										Software reset: This bit is not cleared automatically.
			NORMAL	0								Normal mode.
			KEY	1								The Isolated Key Generation logic and the keys are reset.

IKG.HWCONFIG

Address offset: 0x302C

HwConfig register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				K	K	K	K	J	J	J	J	I	I	I	I	H	H	H	H	G	G	G	F	E	E	D	C	B	B	B	B	A	A	A	A
Reset 0xCC4C8312				1	1	0	0	1	1	0	0	0	1	0	0	1	1	0	0	1	0	0	0	0	0	1	1	0	0	0	1	0	0	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	NBSYMKEYS										Number of Symmetric Keys generated.
B	R	NBPRIVKEYS										Number of Private Keys generated.
C	R	IKGCM										Countermeasures for IKG operations are implemented when 1.
D	R	HWHEALTHTEST										CTR_DRBG health test is implemented when 1.
E	R	CURVE										ECC curve for IKG (input). Note: value 3 is reserved
			P256	0								P256.
			P384	1								P384.
			P521	2								P521.
F	R	DF										Derivation function is implemented in the CTR_DRBG when 1.
G	R	KEYSIZE										AES Key Size support for the AES Core embedded in the CTR_DRBG. [0]: supports AES128 when 1 [1]: supports AES192 when 1 [2]: supports AES256 when 1
			AES128	1								supports AES128
			AES192	2								supports AES192
			AES256	4								supports AES256
H	R	ENTROPYINPUTLENGTH										Value of g_entropy_input_length/32.
I	R	NONCELENGTH										Value of g_nonce_length/32.
J	R	PERSONALIZATIONSTRINGLENGTH										Value of g_personalization_string_length/32.
K	R	ADDITIONALINPUTLENGTH										Value of g_additional_input_length/32.