TAD — Trace and debug control

Configuration interface for trace and debug

Please refer to the Trace section for more information about how to configure the trace and debug interface.

Note: When the trace port is enabled, all pins assigned to the trace port are acquired by the TAD peripheral and cannot be used for GPIO or other functions. This applies even when using the serial trace mode (SWO). See Pin assignment chapter for more information.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
TAD : S TAD : NS	GLOBAL	0x50053000 0x40053000	US	S	NA	No	Trace and debug control

Register overview


Register	Offset	Description
SYSPWRUPREQ	0x400	System power-up request
DBGPWRUPREQ	0x404	Debug power-up request
ENABLE	0x500	Enable debug domain and aquire selected GPIOs
TRACEPORTSPEED	0x518	Trace port speed This register is retained.

SYSPWRUPREQ

Address offset: 0x400

System power-up request


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ACTIVE										Activate power-up request
			NotActive	0								Power-up request not active
			Active	1								Power-up request active

DBGPWRUPREQ

Address offset: 0x404

Debug power-up request


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ACTIVE										Activate power-up request
			NotActive	0								Power-up request not active
			Active	1								Power-up request active

ENABLE

Address offset: 0x500

Enable debug domain and aquire selected GPIOs


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE
			DISABLED	0								Disable debug domain and release selected GPIOs
			ENABLED	1								Enable debug domain and aquire selected GPIOs

TRACEPORTSPEED (Retained)

Address offset: 0x518

Trace port speed

This register is retained.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TRACEPORTSPEED										Trace port speed is divided from CPU clock. The TRACECLK pin output will be divided again by two from the trace port clock.
			DIV1	0								Trace port speed equals CPU clock
			DIV2	1								Trace port speed equals CPU clock divided by 2
			DIV4	2								Trace port speed equals CPU clock divided by 4
			DIV32	3								Trace port speed equals CPU clock divided by 32