SWDP Electrical specification

SW-DP

SymbolDescriptionMin.Typ.Max.Units
Rpull

Internal SWDIO and SWDCLK pull up/down resistance

14kΩ
fSWDCLK

SWDCLK frequency

0.1258MHz
tSUI

SWDIO input setup before SWDCLK

20ns
tHK

SWDIO input hold after SWDCLK

1ns
tVO

SWDCLK to SWDIO output valid

36ns
tHO

SWDIO output hold after SWDCLK

5ns
Figure 1. SWD timing diagram
SWD timing diagram

Trace port

SymbolDescriptionMin.Typ.Max.Units
Tcyc

Clock period, as defined by Arm in Embedded Trace Macrocell Architecture Specification

15.625250ns