TWIM Electrical specification

TWIM interface electrical specifications

SymbolDescriptionMin.Typ.Max.Units
fTWIM,SCL

Bit rates for TWIM1

1001000kbps
tTWIM,START

Time from STARTRX/STARTTX task to transmission started

1.5µs
1 High bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO — General purpose input/output for more details.

Two Wire Interface Master (TWIM) timing specifications

SymbolDescriptionMin.Typ.Max.Units
tTWIM,SU_DATI

Input data setup time before positive edge on SCL – all modes

20ns
tTWIM,HD_DATO

Output data hold time after negative edge on SCL – 100, 250 and 400 kbps

500625ns
tTWIM,HD_STA,100kbps

TWIM master hold time for START and repeated START condition, 100 kbps

10000ns
tTWIM,HD_STA,250kbps

TWIM master hold time for START and repeated START condition, 250 kbps

4000ns
tTWIM,HD_STA,400kbps

TWIM master hold time for START and repeated START condition, 400 kbps

2400ns
tTWIM,SU_STO,100kbps

TWIM master setup time from SCL high to STOP condition, 100 kbps

5000ns
tTWIM,SU_STO,250kbps

TWIM master setup time from SCL high to STOP condition, 250 kbps

2000ns
tTWIM,SU_STO,400kbps

TWIM master setup time from SCL high to STOP condition, 400 kbps

1250ns
tR,100kbps

Rise time of both SDA and SCL signals, 100kbps

1000ns
tF,100kbps

Fall time of both SDA and SCL signals, 100kbps

300ns
tR,400kbps

Rise time of both SDA and SCL signals, 400kbps

300ns
tF,400kbps

Fall time of both SDA and SCL signals, 400kbps

300ns
tTWIM,BUF,100kbps

TWIM master bus free time between STOP and START conditions, 100 kbps

5200ns
tTWIM,BUF,250kbps

TWIM master bus free time between STOP and START conditions, 250 kbps

2200ns
tTWIM,BUF,400kbps

TWIM master bus free time between STOP and START conditions, 400 kbps

1500ns
Figure 1. TWIM timing diagram, 1 byte transaction
TWIM timing diagram, 1 byte transaction