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Peripheral chapters
Register overview table
Register tables
Registers
Product overview
Block diagram
Memory and package overview
Power domains
Address format
Memory
CPU
CPUC — CPU control
Instantiation
AMBA interconnect (AMBIX)
EasyDMA
CACHE — Instruction/data cache
FICR — Factory information configuration registers
MEMCONF — Memory configuration
RRAMC — Resistive random access memory controller
SICR — Secure information configuration region
SWI — Software interrupts
UICR — User information configuration registers
Power and clock management
System ON mode
System OFF mode
Power supply supervisors
CLOCK — Clock control
OSCILLATORS — Oscillator control
POWER — Power control
REGULATORS — Regulator control
RESET — Reset control
Event system
DPPI latencies
DPPI — Distributed programmable peripheral interconnect
PPIB — PPI Bridge
Security
Memory and peripheral access permissions
TrustZone security
Immutable boot region
Security attributes
Security fault
Peripherals with split security access
Physical security
CRACEN — Cryptographic accelerator engine
GLITCHDET — Voltage glitch detectors
KMU — Key management unit
MPC — Memory Privilege Controller
SPU — System protection unit
TAMPC — Tamper controller
Peripherals
Peripheral interface
Instantiation
AAR — Accelerated address resolver
CCM — AES CCM mode encryption
COMP — Comparator
ECB — AES electronic codebook mode encryption
EGU — Event generator unit
GPIO — General purpose input/output
GPIOTE — GPIO tasks and events
GRTC — Global real-time counter
I2S — Inter-IC sound interface
LPCOMP — Low-power comparator
NFCT — Near field communication tag
PDM — Pulse density modulation interface
PWM — Pulse width modulation
QDEC — Quadrature decoder
RADIO — 2.4 GHz radio
SAADC — Successive approximation analog-to-digital converter
SPIM — Serial peripheral interface controller with EasyDMA
SPIS — Serial peripheral interface target with EasyDMA
TEMP — Temperature sensor
TIMER — Timer/counter
TWIM — I2C compatible two-wire interface controller with EasyDMA
TWIS — I2C compatible two-wire interface target with EasyDMA
UARTE — Universal asynchronous receiver/transmitter with EasyDMA
VPR — RISC-V CPU
WDT — Watchdog timer
Debug and trace
Debug access port
Access port protection
Debug Interface mode
Real-time debug
Trace
CTRL-AP — Control access port
TAD — Trace and debug control
ETM — Embedded trace macrocell
TPIU — Trace port interface unit
Pin assignments
QFN40 (QDAA) package
QFN48 (QFAA) package
QFN52 (QGAA) package
CSP47 (CAAA) package
Reference circuitry
Package thermal characteristics
Radio equivalence
Current consumption
CLOCK Electrical specification
COMP Electrical specification
CPU Electrical specification
GPIO Electrical specification
I2S Electrical specification
LPCOMP Electrical specification
NFCT Electrical specification
OSCILLATORS Electrical specification
PPI Electrical specification
PDM Electrical specification
QDEC Electrical specification
RADIO Electrical specification
REGULATORS Electrical specification
RESET Electrical specification
RRAMC Electrical specification
SAADC Electrical specification
SPIM Electrical specification
SPIS Electrical specification
SWDP Electrical specification
TEMP Electrical specification
TWIM Electrical specification
TWIS Electrical specification
UARTE Electrical specification
WDT Electrical specification
Recommended operating conditions
Extended operating temperature
CSP light sensitivity
Absolute maximum ratings
Device marking
Order code
Code ranges and values
Product options
Preprogrammed firmware
Legal notices

Device marking

The nRF54L15/10/05 package is marked as shown in the following figure.

Figure 1. Device marking

See the inner box label and outer box label for more information regarding the box label format.

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