Memory
The CPU and peripherals with EasyDMA can access memory through the AMBIX interconnects. The same interconnect is used by the CPU to access peripheral registers. The following figure is a simplified interconnect diagram.
See Block diagram, AMBA interconnect (AMBIX), and EasyDMA for more information about the AMBIX interconnects and EasyDMA.
RAM and RRAM memory regions are protected with TrustZone® security and are secure after reset. Memory regions can be configured to be non-secure by using MPC — Memory Privilege Controller.
RAM — Random access memory
The device RAM has sections arranged in one contiguous memory range, accessible from both the CPU and peripherals.
Each RAM sections has separate power control for System ON and System OFF mode. This preserves RAM contents in sleep modes or powers off RAM to save power. The sections are illustrated in Memory layout, and the register interface is described in MEMCONF — Memory configuration.
- ProtectedRAM is used for secure key storage.
- VPR saved context is used by VPR to store and restore the context of the VPR during hibernation sleep.
NVM — Non-volatile memory
The CPU can read from non-volatile memory (RRAM) an unlimited number of times, but is restricted in how it writes to memory and the number of writes it can perform.
Writing to RRAM is managed by the RRAM controller (RRAMC), see RRAMC — Resistive random access memory controller.
The Arm® Cortex®-M33 CPU can access RRAM using the C-AHB (code) bus as shown in Memory layout. The code bus (C-AHB) interface is used for any instruction fetch or data access fetch to the code region of the Arm memory model. C-AHB bus access is cached, see CACHE — Instruction/data cache.
RRAM can also be accessed by FLPR. FLPR does not share the instruction cache with the Cortex-M33; it has its own built-in, dedicated cache that is only available to VPR. The regular CACHE — Instruction/data cache is dedicated to the Cortex-M33 and is not available to FLPR.
Memory map
The complete memory map is shown in the following figure.
Instantiation
| ID | Base address | Instance | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
| 64 | 0x50040000 | SPU00 | HF | S | NA | No | System protection unit SPU00 |
| 65 | 0x50041000 | MPC00 | HF | S | NA | No | Memory privilege controller MPC00 |
| 66 | 0x50042000 | US | S | NA | Yes | DPPI controller DPPIC00 | |
| 68 | 0x50044000 | US | S | NA | No | PPI bridge PPIB00 | |
| 69 | 0x50045000 | US | S | NA | No | PPI bridge PPIB01 | |
| 73 | 0x50049000 | KMU | HF | S | NSA | No | Key management unit |
| 74 | 0x5004A000 | US | S | SA | No | Accelerated address resolver 00 | |
| 74 | 0x5004A000 | US | S | SA | No | AES CCM mode encryption CCM00, running of HCLKCORE | |
| 75 | 0x5004B000 | US | S | SA | No | AES ECB mode encryption 00 When configuring this peripheral's DMA security using SPU configuration (DMASEC field of SPU->PERIPH[apb_slave_index]), use apb_slave_index 10 (same as AAR00 and CCM00) | |
| 76 | 0x5004C000 | US | NS | NA | No | FLPR - VPR peripheral registers | |
| 78 | 0x5004E000 | GLITCHDET | HF | S | NA | No | Glitch detectors |
| 78 | 0x5004E000 | RRAMC | HF | S | NA | No | RRAM Non-Volatile Memory Controller |
| 82 | 0x50052000 | US | S | NSA | No | Control access port CPU side | |
| 83 | 0x50053000 | US | S | NA | No | Trace and debug control | |
| 85 | 0x50055000 | US | S | NA | No | Timer TIMER00 | |
| 88 | 0x50058000 | US | S | NA | No | Event generator unit EGU00 | |
| 89 | 0x50059000 | CRACEN | HF | S | NSA | No | Crypto accelerator |
| 128 | 0x50080000 | SPU10 | HF | S | NA | No | System protection unit SPU10 |
| 130 | 0x50082000 | US | S | NA | Yes | DPPI controller DPPIC10 | |
| 131 | 0x50083000 | US | S | NA | No | PPI bridge PPIB10 | |
| 132 | 0x50084000 | US | S | NA | No | PPI bridge PPIB11 | |
| 133 | 0x50085000 | US | S | NA | No | Timer TIMER10 | |
| 135 | 0x50087000 | US | S | NA | No | Event generator unit EGU10 | |
| 138 | 0x5008A000 | US | S | SA | No | 2.4 GHz radio RADIO See pinout for GPIO options for DFE antenna switch control | |
| 192 | 0x500C0000 | SPU20 | HF | S | NA | No | System protection unit SPU20 |
| 194 | 0x500C2000 | US | S | NA | Yes | DPPI controller DPPIC20 | |
| 195 | 0x500C3000 | US | S | NA | No | PPI bridge PPIB20 | |
| 196 | 0x500C4000 | US | S | NA | No | PPI bridge PPIB21 | |
| 197 | 0x500C5000 | US | S | NA | No | PPI bridge PPIB22 | |
| 198 | 0x500C6000 | US | S | SA | No | SPI controller SPIM20 | |
| 198 | 0x500C6000 | US | S | SA | No | SPI peripheral SPIS20 | |
| 198 | 0x500C6000 | US | S | SA | No | Two-wire interface controller TWIM20 | |
| 198 | 0x500C6000 | US | S | SA | No | Two-wire interface target TWIS20 | |
| 198 | 0x500C6000 | US | S | SA | No | Universal asynchronous receiver/transmitter UARTE20 | |
| 199 | 0x500C7000 | US | S | SA | No | SPI controller SPIM21 | |
| 199 | 0x500C7000 | US | S | SA | No | SPI peripheral SPIS21 | |
| 199 | 0x500C7000 | US | S | SA | No | Two-wire interface controller TWIM21 | |
| 199 | 0x500C7000 | US | S | SA | No | Two-wire interface target TWIS21 | |
| 199 | 0x500C7000 | US | S | SA | No | Universal asynchronous receiver/transmitter UARTE21 | |
| 201 | 0x500C9000 | US | S | NA | No | Event generator unit EGU20 | |
| 202 | 0x500CA000 | US | S | NA | No | Timer TIMER20 | |
| 203 | 0x500CB000 | US | S | NA | No | Timer TIMER21 | |
| 204 | 0x500CC000 | US | S | NA | No | Timer TIMER22 | |
| 205 | 0x500CD000 | US | S | NA | No | Timer TIMER23 | |
| 206 | 0x500CE000 | US | S | NA | No | Timer TIMER24 | |
| 207 | 0x500CF000 | US | S | NA | No | Memory Configuration MEMCONF | |
| 213 | 0x500D5000 | US | S | SA | No | Successive approximation analog-to-digital converter SAADC | |
| 215 | 0x500D7000 | US | S | NA | No | Temperature sensor TEMP | |
| 216 | 0x500D8200 | US | S | NA | Yes | General purpose input and output, port P1 | |
| 218 | 0x500DA000 | US | S | NA | Yes | 8 channels and 2 interrupts for GPIO port P1 GPIO tasks and events GPIOTE20 | |
| 226 | 0x500E2000 | US | S | NA | Yes | Global RTC GRTC | |
| 239 | 0x500EF000 | TAMPC | HF | S | NA | No | Tamper controller TAMPC |
| 256 | 0x50100000 | SPU30 | HF | S | NA | No | System protection unit SPU30 |
| 258 | 0x50102000 | US | S | NA | Yes | DPPI controller DPPIC30 | |
| 259 | 0x50103000 | US | S | NA | No | PPI bridge PPIB30 | |
| 260 | 0x50104000 | US | S | SA | No | SPI controller SPIM30 | |
| 260 | 0x50104000 | US | S | SA | No | SPI peripheral SPIS30 | |
| 260 | 0x50104000 | US | S | SA | No | Two-wire interface controller TWIM30 | |
| 260 | 0x50104000 | US | S | SA | No | Two-wire interface target TWIS30 | |
| 260 | 0x50104000 | US | S | SA | No | Universal asynchronous receiver/transmitter UARTE30 | |
| 262 | 0x50106000 | US | S | NA | No | Comparator COMP | |
| 262 | 0x50106000 | US | S | NA | No | Low-power comparator LPCOMP | |
| 264 | 0x50108000 | WDT30 | HF | S | NA | No | Watchdog timer WDT30 |
| 265 | 0x50109000 | US | S | NA | No | Watchdog timer WDT31 | |
| 266 | 0x5010A000 | US | S | NA | Yes | General purpose input and output, port P0 | |
| 268 | 0x5010C000 | US | S | NA | Yes | 4 channels and 2 interrupts for GPIO port P0 GPIO tasks and events GPIOTE30 | |
| 270 | 0x5010E000 | US | S | NA | No | Clock control | |
| 270 | 0x5010E000 | US | S | NA | No | Power control | |
| 270 | 0x5010E000 | US | S | NA | No | Reset status | |
| 288 | 0x50120000 | US | S | NA | No | Oscillator control | |
| 288 | 0x50120000 | US | S | NA | No | Regulator control | |
| N/A | 0x00FFC000 | FICR | HF | NS | NA | No | Factory information configuration |
| N/A | 0x00FFD000 | UICR | HF | S | NA | No | User information configuration |
| N/A | 0x00FFE000 | SICR | HF | S | NA | No | Secure information configuration region |
| N/A | 0x50010000 | CRACENCORE | HF | S | NSA | No | CRACEN core |