CPUC — CPU control

CPUC controls elements of the Arm® Cortex®-M33 processor such as enabling floating-point exceptions. It is also able to lock certain features of the CPU and prevent them from being modified.

CPUC can generate events and CPU interupts for exceptions in the floating point unit (FPU), as shown in the following block diagram. Examples of such exceptions are divide-by-zero or floating-point overflow.

Block diagram shows events generated by CPUC — Figure 1. Block diagram

CPUC holds a CPU identifier CPUID, used in the system to uniquely identify the processing unit of a core.

In addition, CPUC holds a LOCK register, which is used to lock certain CPU features and prevent them from being modified. One example is the LOCK.LOCKSAU field. When set to Locked, this prevents further modifications to the SAU registers.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
CPUC	APPLICATION	0xE0080000	HF	S	NA	No	Cortex-M33 configuration

Register overview


Register	Offset	Description
EVENTS_FPUIOC	0x100	An invalid operation exception has occurred in the FPU.
EVENTS_FPUDZC	0x104	A floating-point divide-by-zero exception has occurred in the FPU.
EVENTS_FPUOFC	0x108	A floating-point overflow exception has occurred in the FPU.
EVENTS_FPUUFC	0x10C	A floating-point underflow exception has occurred in the FPU.
EVENTS_FPUIXC	0x110	A floating-point inexact exception has occurred in the FPU.
EVENTS_FPUIDC	0x114	A floating-point input denormal exception has occurred in the FPU.
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
LOCK	0x500	Register to lock the certain parts of the CPU from being modified.
CPUID	0x504	The identifier for the CPU in this subsystem.

EVENTS_FPUIOC

Address offset: 0x100

An invalid operation exception has occurred in the FPU.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_FPUIOC										An invalid operation exception has occurred in the FPU.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_FPUDZC

Address offset: 0x104

A floating-point divide-by-zero exception has occurred in the FPU.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_FPUDZC										A floating-point divide-by-zero exception has occurred in the FPU.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_FPUOFC

Address offset: 0x108

A floating-point overflow exception has occurred in the FPU.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_FPUOFC										A floating-point overflow exception has occurred in the FPU.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_FPUUFC

Address offset: 0x10C

A floating-point underflow exception has occurred in the FPU.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_FPUUFC										A floating-point underflow exception has occurred in the FPU.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_FPUIXC

Address offset: 0x110

A floating-point inexact exception has occurred in the FPU.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_FPUIXC										A floating-point inexact exception has occurred in the FPU.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_FPUIDC

Address offset: 0x114

A floating-point input denormal exception has occurred in the FPU.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_FPUIDC										A floating-point input denormal exception has occurred in the FPU.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FPUIOC										Enable or disable interrupt for event FPUIOC
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	FPUDZC										Enable or disable interrupt for event FPUDZC
			Disabled	0								Disable
			Enabled	1								Enable
C	RW	FPUOFC										Enable or disable interrupt for event FPUOFC
			Disabled	0								Disable
			Enabled	1								Enable
D	RW	FPUUFC										Enable or disable interrupt for event FPUUFC
			Disabled	0								Disable
			Enabled	1								Enable
E	RW	FPUIXC										Enable or disable interrupt for event FPUIXC
			Disabled	0								Disable
			Enabled	1								Enable
F	RW	FPUIDC										Enable or disable interrupt for event FPUIDC
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	FPUIOC										Write '1' to enable interrupt for event FPUIOC
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	FPUDZC										Write '1' to enable interrupt for event FPUDZC
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1S	FPUOFC										Write '1' to enable interrupt for event FPUOFC
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW W1S	FPUUFC										Write '1' to enable interrupt for event FPUUFC
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW W1S	FPUIXC										Write '1' to enable interrupt for event FPUIXC
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW W1S	FPUIDC										Write '1' to enable interrupt for event FPUIDC
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	FPUIOC										Write '1' to disable interrupt for event FPUIOC
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1C	FPUDZC										Write '1' to disable interrupt for event FPUDZC
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1C	FPUOFC										Write '1' to disable interrupt for event FPUOFC
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW W1C	FPUUFC										Write '1' to disable interrupt for event FPUUFC
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW W1C	FPUIXC										Write '1' to disable interrupt for event FPUIXC
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW W1C	FPUIDC										Write '1' to disable interrupt for event FPUIDC
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

LOCK

Address offset: 0x500

Each bit can only be written once and can only be changed from 0 to 1.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	LOCKVTORAIRCRS										Locks both the Vector table Offset Register (VTOR) and Application Interrupt and Reset Control Register (AIRCR) for secure mode.
			NotLocked	0								Both VTOR and AIRCR can be changed.
			Locked	1								Prevents changes to both VTOR and AIRCR.
B	RW	LOCKVTORNS										Locks the Vector table Offset Register (VTOR) for non-secure mode.
			NotLocked	0								VTOR can be changed.
			Locked	1								Prevents changes to VTOR.
C	RW	LOCKMPUS										Locks the Memory Protection Unit (MPU) for secure mode.
			NotLocked	0								MPU registers can be changed.
			Locked	1								Prevents changes to MPU registers.
D	RW	LOCKMPUNS										Locks the Memory Protection Unit (MPU) for non secure mode.
			NotLocked	0								MPU registers can be changed.
			Locked	1								Prevents changes to MPU registers.
E	RW	LOCKSAU										Locks the Security Attribution Unit (SAU)
			NotLocked	0								SAU registers can be changed.
			Locked	1								Prevents changes to SAU registers.

CPUID

Address offset: 0x504

The identifier for the CPU in this subsystem.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CPUID										The CPU identifier.