TAMPC — Tamper controller

The tamper controller peripheral handles input from internal and external physical attack detectors and controls the device response.

The following figure shows an overview of the TAMPC detectors, input, and output.

TAMPC implements the following physical security features:

Detection of external tampering attacks
- Detector supporting an active driven shield mounted on a PCB that is on top of a device
Detection of fault injection attacks (voltage glitching, electromagnetic fault injection, etc.)
- Signal protector to guard critical configuration signals
- Glitch detectors to protect internal logic
- Built-in self-check for correctness inside the CRACEN

The tamper detectors are divided into two categories: external and internal. The external detectors rely on external stimuli through dedicated GPIO pins, and the internal detectors rely on internal signals not exposed outside the device package.

External tamper detectors

A tamper attack detected by any of the external tamper detectors indicates that a break-in attack is ongoing. This could include breaking the product encapsulation. This is detected through the external active shield detectors.

Internal tamper detectors

A tamper attack detected by an internal tamper detector indicates that the device's internal logic could be affected by the attack, the system state could be compromised, and thus not to be trusted. Recommended operation is to utilize the TAMPC automatic system wide reset feature, see PROTECT.INTRESETEN.CTRL. This ensures the device is operating in a safe and known state after an attack has been detected. The automatic reset from TAMPC triggers SECTAMPER to be set in the reset reason register. The device should on the following reset check for SECTAMPER in the reset reason register and take necessary action.

Active shield

TAMPC supports an active shield to protect against physical access to the device and its connections on the PCB level.

The active shield detector is enabled using the register PROTECT.ACTIVESHIELD.CTRL. The active shield detector has a number of channels. Depending on its configuration, TAMPC will react when a channel in the active shield is broken, meaning there is a mismatch between the input and output signal of an enabled channel in the active shield. A broken channel detected in the active shield causes one of the following to occur:

A TAMPC event is generated.
A chip reset is triggered and the SECTAMPER value in the reset reason register indicates what happened, depending on the status of the register PROTECT.EXTRESETEN.CTRL.

A channel in the active shield detector consists of a signal propagating from an output pin to an input pin. The channels are enabled using the CH[i] fields in the register ACTIVESHIELD.CHEN. The GPIO pins reserved for the active shield detector channels must be configured before the channels are ready for use. Pin direction and CTRLSEL must be set according to the register interface in the GPIO peripheral. For more information about reserved active shield detector pins, see Pin assignments. Pins reserved for the active shield detector can be used as generic GPIO pins when the channel is unused.

The active shield detector contains a Pseudo-Random Bit Sequence (PRBS) generator. A PRBS signal is generated on an output pin at each rising edge of the 32 KHz clock. The signal is routed through an external shield to an input pin. The signal on the input pin is sampled on the falling edge of the 32KHz clock. If the sampled signal does not match the transmitted signal, a channel in the external shield is assumed broken and a tamper event is generated.

CRACEN tamper detector

The cryptographic accelerator engine (CRACEN) implements a separate tamper detector mechanism. This tamper detector is always enabled.

CRACEN has security countermeasures and notifies TAMPC if tampering is detected during its operations. TAMPC will react according to the register setting in PROTECT.CRACENTAMP.CTRL and one of the following will occur:

A TAMPC event is generated.
A chip reset is triggered and the SECTAMPER value in the reset reason register indicates what happened, depending on the status of the register PROTECT.INTRESETEN.CTRL.

The internal tamper reset enable signal INTRESETEN is enabled from reset.

For more information about CRACEN countermeasures, see CRACEN — Cryptographic accelerator engine.

Glitch detector

The device implements glitch detectors to protect against fault injection attacks.

Detectors are strategically placed to detect fault injection attacks. The detectors are designed and tuned to trigger before logic fails enabling the digital logic to react before an injected fault is propagated through the system.

The glitch detectors are enabled from reset and can be disabled for debugging using

When an internal tamper event is detected, one of the following will occur:

A TAMPC EVENT is generated.
A chip reset is triggered and the SECTAMPER value in the reset reason register indicates what happened, depending on the status of the register PROTECT.INTRESETEN.CTRL.

Signal protector

The device implements detectors to protect selected signals that control critical device features.

The signal protector implements one detector per protected signal to detect unintentional value changes in that signal. The detector notifies TAMPC if a protected signal changes value caused by tampering. The detectors are enabled from reset and can be disabled using the register , which is for debugging purposes only. A detected unintentional value change in any of the protected signals leads to an internal tamper event where one of the following occur:

A TAMPC event is generated.
A chip reset is triggered and the SECTAMPER value in the reset reason register indicates what happened, depending on the status of the register PROTECT.INTRESETEN.CTRL.

The INTRESETEN register is enabled from reset. The PROTECT.<component>.STATUS registers indicate which protected signal had an unintentional value change when the register INTENRESETEN is disabled.

The signal protector implements a two stage write cycle to change the value of a protected signal, in addition to a required write key which must be included for all register writes. The two stages are the following:

Initial register write to clear the write protection.
Register write to change the signal's value.

Write Clear to the WRITEPROTECTION field in the PROTECT.<component>.CTRL register to clear the write protection in the first register write. Then write to the VALUE and LOCK fields in the next register write operation.

Note: It is required to clear the WRITEPROTECTION field before any updates to the VALUE and LOCK fields are accepted by the register.

The write protection is automatically re-enabled after the subsequent write to change the VALUE field when the register write does not include the Clear value in the WRITEPROTECTION field.

The LOCK field controls a lock feature which prevents further updates to the VALUE and LOCK fields until a reset with the required reset source for the specific signal is issued.

A WRITEERROR event is generated for any of the following conditions:

Register write does not have the correct write key
Write protection is active and the write operation does not contain the value to clear the write protection
The lock is enabled

The sequence to change the VALUE or LOCK fields in the PROTECT.<component>.CTRL registers is as follows:

Write Clear to the WRITEPROTECTION field and KEY to the KEY field.
Write Disabled to the WRITEPROTECTION field, KEY to the KEY field, and KEY to the desired LOCK and VALUE fields.

Debugger signals

TAMPC provides protection for the following Arm® CoreSight™ debugger signals.

Table 1. TAMPC protected debugger signals
Signal	Name	Notes
NIDEN	Non-Invasive Debug Enable	ETM/ITM trace and other non-halting debug methods
DBGEN	Invasive Debug Enable	The debugger may halt the CPU for debug purposes
SPNIDEN	Secure Privileged Non-Invasive Debug Enable	Same as NIDEN with a secure TrustZone® security attribute
SPIDEN	Secure Privileged Debug Enable	Same as DBGEN with a secure TrustZone security attribute

See the appropriateArm CoreSight Technical Reference manual for details on these signals.

For more information about using the protected debugger signals, see Debug and trace.

TAMPC reset behavior

TAMPC registers are reset by different sources.

Protected signals in TAMPC are divided into the following reset source categories.

Category 1 – Brownout reset, power-on reset
Category 2 – Pin reset and TAMPC reset
Category 3 – Watchdog timer reset, CPU lockup reset, System reset request, and Wake-up from System OFF reset

For more information about reset sources, see RESET — Reset control.

Table 2. TAMPC protected signals
			Reset source
Register	Function	Reset value	Cat 1	Cat 2	Cat 3
PROTECT.DOMAIN[0].DBGEN	Allow invasive debugging in non-secure mode of Arm Cortex-M33.	0	x	x
PROTECT.DOMAIN[0].NIDEN	Allow non-invasive debugging in non-secure mode of Arm Cortex-M33.	0	x	x
PROTECT.DOMAIN[0].SPIDEN	Allow invasive debugging in secure mode of Arm Cortex-M33.	0	x	x
PROTECT.DOMAIN[0].SPNIDEN	Allow non-invasive debugging in secure mode of Arm Cortex-M33.	0	x	x
PROTECT.AP[0].DBGEN	Allow debugging of FLPR RISC-V CPU.	0	x	x
PROTECT.ACTIVESHIELD	Enable active shield detector.	0	x	x	x
PROTECT.CRACENTAMP	Enable CRACEN tamper detector.	1	x	x	x
PROTECT.GLITCHSLOWDOMAIN	Enable slow domain glitch detector.	1	x	x	x
PROTECT.GLITCHFASTDOMAIN	Enable fast domain glitch detector.	1	x	x	x
PROTECT.EXTRESETEN	Enable automatic reset from external tamper detectors events.	0	x	x	x
PROTECT.INTRESETEN	Enable automatic reset from internal tamper detector events.	1	x	x	x
PROTECT.ERASEPROTECT	Allow device erase using CTRL-AP and RRAMC.	0	x	x	x

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
TAMPC	GLOBAL	0x500EF000	HF	S	NA	No	Tamper controller TAMPC

Configuration


Instance	Domain	Configuration
TAMPC	GLOBAL	For the active shield function, use dedicated pins on P1

Register overview


Register	Offset	Description
EVENTS_TAMPER	0x100	Tamper controller detected an error.
EVENTS_WRITEERROR	0x104	Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT.
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
INTPEND	0x30C	Pending interrupts
STATUS	0x400	The tamper controller status.
ACTIVESHIELD.CHEN	0x404	Active shield detector channel enable register.
PROTECT.DOMAIN[n].DBGEN.CTRL	0x500	Control register for invasive (halting) debug enable for the local debug components within domain n.
PROTECT.DOMAIN[n].DBGEN.STATUS	0x504	Status register for invasive (halting) debug enable for domain n.
PROTECT.DOMAIN[n].NIDEN.CTRL	0x508	Control register for non-invasive debug enable for the local debug components within domain n.
PROTECT.DOMAIN[n].NIDEN.STATUS	0x50C	Status register for non-invasive debug enable for domain n.
PROTECT.DOMAIN[n].SPIDEN.CTRL	0x510	Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n.
PROTECT.DOMAIN[n].SPIDEN.STATUS	0x514	Status register for secure priviliged invasive (halting) debug enable for domain n.
PROTECT.DOMAIN[n].SPNIDEN.CTRL	0x518	Control register for secure priviliged non-invasive debug enable for the local debug components within domain n.
PROTECT.DOMAIN[n].SPNIDEN.STATUS	0x51C	Status register for secure priviliged non-invasive debug enable for domain n.
PROTECT.AP[n].DBGEN.CTRL	0x700	Control register to enable invasive (halting) debug in domain ns access port.
PROTECT.AP[n].DBGEN.STATUS	0x704	Status register for invasive (halting) debug enable for domain ns access port.
PROTECT.ACTIVESHIELD.CTRL	0x900	Control register for active shield detector enable signal.
PROTECT.ACTIVESHIELD.STATUS	0x904	Status register for active shield detector enable signal.
PROTECT.CRACENTAMP.CTRL	0x938	Control register for CRACEN tamper detector enable signal.
PROTECT.CRACENTAMP.STATUS	0x93C	Status register for CRACEN tamper detector enable signal.
PROTECT.GLITCHSLOWDOMAIN.CTRL	0x940	Control register for slow domain glitch detectors enable signal.
PROTECT.GLITCHSLOWDOMAIN.STATUS	0x944	Status register for slow domain glitch detectors enable signal.
PROTECT.GLITCHFASTDOMAIN.CTRL	0x948	Control register for fast domain glitch detectors enable signal.
PROTECT.GLITCHFASTDOMAIN.STATUS	0x94C	Status register for fast domain glitch detectors enable signal.
PROTECT.EXTRESETEN.CTRL	0x970	Control register for external tamper reset enable signal.
PROTECT.EXTRESETEN.STATUS	0x974	Status register for external tamper reset enable signal.
PROTECT.INTRESETEN.CTRL	0x978	Control register for internal tamper reset enable signal.
PROTECT.INTRESETEN.STATUS	0x97C	Status register for internal tamper reset enable signal.
PROTECT.ERASEPROTECT.CTRL	0x980	Control register for erase protection.
PROTECT.ERASEPROTECT.STATUS	0x984	Status register for eraseprotect.

EVENTS_TAMPER

Address offset: 0x100

Tamper controller detected an error.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_TAMPER										Tamper controller detected an error.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_WRITEERROR

Address offset: 0x104

Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_WRITEERROR										Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TAMPER										Enable or disable interrupt for event TAMPER
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	WRITEERROR										Enable or disable interrupt for event WRITEERROR
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	TAMPER										Write '1' to enable interrupt for event TAMPER
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	WRITEERROR										Write '1' to enable interrupt for event WRITEERROR
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	TAMPER										Write '1' to disable interrupt for event TAMPER
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1C	WRITEERROR										Write '1' to disable interrupt for event WRITEERROR
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTPEND

Address offset: 0x30C

Pending interrupts


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	TAMPER										Read pending status of interrupt for event TAMPER
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
B	R	WRITEERROR										Read pending status of interrupt for event WRITEERROR
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending

STATUS

Address offset: 0x400

The tamper controller status.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.

Note: The glitch detectors must be reset using their CTRL registers before the STATUS register bits for glitch detectors can be cleared. The glitch detector continuously drives its output status signal to the STATUS register, hence clearing only the STATUS register is not sufficient.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				H	G	F	E				D			C	B				A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ACTIVESHIELD										Active shield detector detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.
B	RW W1C	PROTECT										Error detected for the protected signals.
			NotDetected	0								Not detected.
			Detected	1								Detected.
C	RW W1C	CRACENTAMP										CRACEN detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.
D	RW W1C	GLITCHSLOWDOMAIN[i] (i=0..0)										Slow domain glitch detector i detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.
E-H	RW W1C	GLITCHFASTDOMAIN[i] (i=0..3)										Fast domain glitch detector i detected an error.
			NotDetected	0								Not detected.
			Detected	1								Detected.

ACTIVESHIELD.CHEN

Address offset: 0x404

Active shield detector channel enable register.

Pins reserved for the active shield channels must be configured before the channels can be used. Pins reserved for unused channels can be used as GPIO.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-B	RW	CH[i] (i=0..1)										Enable or disable active shield channel i.
			Disabled	0								Disable channel.
			Enabled	1								Enable channel.

PROTECT.DOMAIN[n].DBGEN.CTRL

Address offset: 0x500 + (n × 0x20)

Control register for invasive (halting) debug enable for the local debug components within domain n.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of dbgen signal.
			Low	0								Signal is logic 0, indicating that invasive debug is disabled.
			High	1								Signal is logic 1, indicating that invasive debug is enabled.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.DOMAIN[n].DBGEN.STATUS

Address offset: 0x504 + (n × 0x20)

Status register for invasive (halting) debug enable for domain n.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.DOMAIN[n].NIDEN.CTRL

Address offset: 0x508 + (n × 0x20)

Control register for non-invasive debug enable for the local debug components within domain n.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of niden signal.
			Low	0								Signal is logic 0, indicating that non-invasive debug is disabled.
			High	1								Signal is logic 1, indicating that non-invasive debug is enabled.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.DOMAIN[n].NIDEN.STATUS

Address offset: 0x50C + (n × 0x20)

Status register for non-invasive debug enable for domain n.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.DOMAIN[n].SPIDEN.CTRL

Address offset: 0x510 + (n × 0x20)

Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of spiden signal.
			Low	0								Signal is logic 0, indicating that secure priviliged invasive debug is disabled.
			High	1								Signal is logic 1, indicating that secure priviliged invasive debug is enabled.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.DOMAIN[n].SPIDEN.STATUS

Address offset: 0x514 + (n × 0x20)

Status register for secure priviliged invasive (halting) debug enable for domain n.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.DOMAIN[n].SPNIDEN.CTRL

Address offset: 0x518 + (n × 0x20)

Control register for secure priviliged non-invasive debug enable for the local debug components within domain n.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of spniden signal.
			Low	0								Signal is logic 0, indicating that secure priviliged non-invasive debug is disabled.
			High	1								Signal is logic 1, indicating that secure priviliged non-invasive debug is enabled.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.DOMAIN[n].SPNIDEN.STATUS

Address offset: 0x51C + (n × 0x20)

Status register for secure priviliged non-invasive debug enable for domain n.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.AP[n].DBGEN.CTRL

Address offset: 0x700 + (n × 0x10)

Control register to enable invasive (halting) debug in domain ns access port.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of dbgen signal.
			Low	0								Signal is logic 0, indicating that invasive debug is disabled.
			High	1								Signal is logic 1, indicating that invasive debug is enabled.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.AP[n].DBGEN.STATUS

Address offset: 0x704 + (n × 0x10)

Status register for invasive (halting) debug enable for domain ns access port.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.ACTIVESHIELD

Enable active shield detector.

The active shield pins are dedicated GPIO pins that must be configured as inputs and outputs before use. Each active shield channel has one GPIO for output and one GPIO for input.

PROTECT.ACTIVESHIELD.CTRL

Address offset: 0x900

Control register for active shield detector enable signal.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of active shield enable signal.
			Low	0								Signal is logic 0.
			High	1								Signal is logic 1.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.ACTIVESHIELD.STATUS

Address offset: 0x904

Status register for active shield detector enable signal.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.CRACENTAMP

Enable tamper detector from CRACEN.

Note: Disabling this bit only disables the TAMPC handling of the CRACENTAMP event, it does not disable the CRACEN from generating the CRACENTAMP event.

PROTECT.CRACENTAMP.CTRL

Address offset: 0x938

Control register for CRACEN tamper detector enable signal.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000011				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of CRACEN tamper detector enable signal.
			Low	0								Signal is logic 0.
			High	1								Signal is logic 1.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.CRACENTAMP.STATUS

Address offset: 0x93C

Status register for CRACEN tamper detector enable signal.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.GLITCHSLOWDOMAIN

Enable slow domain glitch detectors.

PROTECT.GLITCHSLOWDOMAIN.CTRL

Address offset: 0x940

Control register for slow domain glitch detectors enable signal.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000011				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of slow domain glitch detectors enable signal.
			Low	0								Signal is logic 0.
			High	1								Signal is logic 1.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.GLITCHSLOWDOMAIN.STATUS

Address offset: 0x944

Status register for slow domain glitch detectors enable signal.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.GLITCHFASTDOMAIN

Enable fast domain glitch detectors.

PROTECT.GLITCHFASTDOMAIN.CTRL

Address offset: 0x948

Control register for fast domain glitch detectors enable signal.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000011				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of fast domain glitch detector's enable signal.
			Low	0								Signal is logic 0.
			High	1								Signal is logic 1.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.GLITCHFASTDOMAIN.STATUS

Address offset: 0x94C

Status register for fast domain glitch detectors enable signal.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.EXTRESETEN

Trigger a reset when tamper is detected by the external tamper detectors.

This reset gives reset reason SECTAMPER

PROTECT.EXTRESETEN.CTRL

Address offset: 0x970

Control register for external tamper reset enable signal.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of external tamper reset enable signal.
			Low	0								Signal is logic 0.
			High	1								Signal is logic 1.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.EXTRESETEN.STATUS

Address offset: 0x974

Status register for external tamper reset enable signal.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.INTRESETEN

Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector.

This reset gives reset reason SECTAMPER

PROTECT.INTRESETEN.CTRL

Address offset: 0x978

Control register for internal tamper reset enable signal.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000011				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of internal tamper reset enable signal.
			Low	0								Signal is logic 0.
			High	1								Signal is logic 1.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.INTRESETEN.STATUS

Address offset: 0x97C

Status register for internal tamper reset enable signal.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.

PROTECT.ERASEPROTECT

Device erase protection.

PROTECT.ERASEPROTECT.CTRL

Address offset: 0x980

Control register for erase protection.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	C	C	C			B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Set value of eraseprotect signal.
			Low	0								Signal is logic 0.
			High	1								Signal is logic 1.
B	W1 W1S	LOCK										Lock this register to prevent changes to the VALUE field until next reset.
			Disabled	0								Lock disabled.
			Enabled	1								Lock enabled.
C	RW	WRITEPROTECTION										The write protection must be cleared to allow updates to the VALUE field. The write protection is cleared by writing CLEAR in a separate write operation prior to updating the VALUE and LOCK fields. The write protection is automatically enabled after the corresponding change to the VALUE field.
			Disabled	0x0								Read: Write protection is disabled.
			Enabled	0x1								Read: Write protection is enabled.
			Clear	0xF								Write: Value to clear write protection.
D	W	KEY										Required write key for upper 16 bits. Must be included in all register write operations.
			KEY	0x50FA								Write key value.

PROTECT.ERASEPROTECT.STATUS

Address offset: 0x984

Status register for eraseprotect.

Note: Unless cleared, the STATUS register will be cumulative. A field is cleared by writing '1' to it.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	ERROR										Error detection status.
			NoError	0								No error detected.
			Error	1								Error detected.