TWIM — I2C compatible two-wire interface controller with EasyDMA

The FREQUENCY register defines the speed at which data is transmitted over the interface. Enumerators for common frequencies, such as K100 or K400, are provided.

The following formula can be used to calculate arbitrary frequencies. Due to the finite resolution of the clock generator, the actual SCL frequency may vary slightly from the calculated value.

Note: The frequency calculation equation is applicable only within the following SCL frequency ranges:

• Fast-mode: 90 kHz to 500 kHz
• Fast-mode plus: 900 kHz to 1100 kHz

Outside of these frequency intervals, the accuracy is not guaranteed.

• FREQUENCY is the value to be used in the TWIM FREQUENCY register.
• f_PCLK is the peripheral clock frequency for the TWIM instance, as defined in Instances.
• desired_frequency is the desired frequency in hertz, such as 100000 or 400000.

TWIM is started by triggering the DMA.TX.START or DMA.RX.START tasks, and stopped by triggering the STOP task. If TWIM is running when the STOP task is triggered, it stops and generates a STOPPED event.

After TWIM starts, the DMA.TX.START and DMA.RX.START tasks must not be triggered again until TWIM has issued a LASTRX, LASTTX, or STOPPED event.

TWIM can be suspended using the SUSPEND task, which is useful when using TWIM in a low priority interrupt context. When TWIM enters the SUSPEND state, it will automatically issue a SUSPENDED event while performing a continuous clock stretching. This continues until a RESUME task is received. TWIM cannot be stopped while it is suspended. The STOP task must be issued after TWIM resumes operation.

If a NACK is clocked in from the target, TWIM generates an ERROR event.

The TWIM peripheral shares registers and other resources with peripherals that have the same ID as TWIM. Therefore, all peripherals that have the same ID as TWIM must be disabled before TWIM can be configured and used.

Disabling shared peripherals will not reset any of the registers that are shared with TWIM. Configure all relevant TWIM registers to ensure they operate correctly.

See the Instantiation table in Instantiation for details on peripherals and their IDs.

EasyDMA is implemented by TWIM in order to access RAM without the CPU.

The RXD.PTR, TXD.PTR, RXD.MAXCNT, and TXD.MAXCNT registers are double-buffered. They are ready for the next transmission immediately after receiving the EVENTS_DMA.RX.READY or EVENTS_DMA.TX.READY event.

The STOPPED event indicates that EasyDMA is finished accessing the buffer in RAM.

See EasyDMA for more detailed information.

A TWIM write sequence is started by triggering the DMA.TX.START task. After the DMA.TX.START task has been triggered, TWIM generates a start condition on the TWI bus. This is followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE = 0, READ = 1).

The target device address the controller wants to write to must match the clocked address. The READ/WRITE bit is followed by an ACK/NACK bit (ACK = 0 or NACK = 1) generated by the target.

After receiving the ACK bit, TWIM clocks out the data bytes found in the transmit buffer located in RAM at the address specified in the TXD.PTR register. Each byte clocked out from TWIM is followed by an ACK/NACK bit clocked in from the target.

A typical TWIM write sequence including clock stretching performed by TWIM following a SUSPEND task is shown in the following figure.

A SUSPENDED event indicates that the SUSPEND task has taken effect.

TWIM will generate a LASTTX event when it starts to transmit the last byte.

TWIM is stopped by triggering the STOP task. To stop TWIM as fast as possible, trigger the task during the transmission of the last byte. The shortcut between LASTTX and STOP can also be used to accomplish this.

TWIM does not stop on its own when the entire RAM buffer has been sent or when an error occurs. The STOP task must be issued, either through the local or PPI shortcut, or in software as part of the error handler.

A TWIM read sequence is started by triggering the DMA.RX.START task. After the DMA.RX.START task has been triggered, TWIM generates a start condition on the TWI bus. This is followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1). The address must match the address of the target device that the controller wants to read from. The READ/WRITE bit is followed by an ACK/NACK bit (ACK = 0 or NACK = 1) generated by the target.

After sending the ACK bit, the TWI target sends data to the controller using the clock generated by TWIM.

Data received will be stored in RAM at the address specified in the RXD.PTR register. TWIM will generate an ACK before the last byte is received from the target. TWIM generates a NACK after the last byte received to indicate that the read sequence will stop.

A typical TWIM read sequence is illustrated in the following figure, including clock stretching performed by TWIM following a SUSPEND task.

A SUSPENDED event indicates that the SUSPEND task has taken effect. This event can be used to synchronize the software.

TWIM generates a LASTRX event when it is ready to receive the last byte. If RXD.MAXCNT > 1, the LASTRX event is generated after sending the ACK of the previously received byte. If RXD.MAXCNT = 1, the LASTRX event is generated after receiving the ACK following the address and READ bit.

TWIM is stopped by triggering the STOP task. This task must be triggered before the NACK bit begins transmission. The STOP task can be triggered at any time during the reception of the last byte. It is recommended to use the shortcut between LASTRX and STOP.

TWIM does not stop on its own when the RAM buffer is full or when an error occurs. The STOP task must be issued, either through a local or PPI shortcut, or in software as part of the error handler.

TWIM cannot be stopped while suspended. The STOP task must be issued after TWIM has been resumed.

A typical repeated start sequence is when TWIM writes two bytes to the target followed by reading four bytes from the target. This example uses shortcuts to perform a simple repeated start sequence, with one write followed by one read. The same approach can be used to perform a repeated start sequence where the sequence is read followed by a write.

The following figure shows an example of a repeated start sequence where TWIM writes two bytes followed by reading four bytes from the target.

If a more complex repeated start sequence is needed, and the TWI firmware drive is serviced in a low priority interrupt, use the SUSPEND task and SUSPENDED event to ensure that the correct tasks are generated at the correct time. A double repeated start sequence using the SUSPEND task to secure safe operation in low priority interrupts is shown in the following figure.

When the peripheral is not needed, stop and disable TWIM for lowest possible power consumption.

When the STOP task is sent, the software must wait until the STOPPED event is received before disabling the peripheral through the ENABLE register. If the peripheral is already stopped, the STOP task is not needed.

The SCL and SDA signals are mapped to physical pins using the PSEL.SCL and PSEL.SDA registers.

These registers and their configurations are only used when TWIM is enabled, and retained while the device is in System ON mode. When the peripheral is disabled, the pins behave as regular GPIOs and are configured according to their respective OUT bit field and PIN_CNF[n] register. Configure registers PSEL.SCL and PSEL.SDA when TWIM is disabled.

Only one peripheral can be assigned to drive a GPIO pin at a time. If more than one peripheral is assigned to a GPIO pin, it could result in unpredictable behavior.

When TWIM is in System OFF mode or disabled, the pins using TWIM must be configured by the GPIO peripheral according to the following table to ensure correct pin behavior.

TWIM has a compare match filter that can watch for a specific sequence of data. This feature is implemented in EasyDMA on the RX channel.

TWIM can generate events or interrupts when the specific data sequence is received. The event EVENTS_DMA.RX.MATCH[n] (n=0..3) is generated when there is a match in the data stream being received. The number of MATCH events can be different for each instance. See Registers for how many MATCH events are implemented per instance.

Register DMA.RX.MATCH.CANDIDATE[n] (n=0..3) configures the pattern for comparison. The filter is enabled with register DMA.RX.MATCH.CONFIG or task TASKS_DMA.RX.ENABLEMATCH[n] (n=0..3).

For detailed information regarding the use of pattern matching in the EasyDMA engine, see .

1000 kbps bit rate is supported when using H0D1 drive strength, 1 kΩ pull-up resistor, and maximum 50 pF bus capacitance. For other bit rates, see the following figure.