VPR — RISC-V CPU

VPR is a small, efficient CPU developed by Nordic Semiconductor.

The VPR implementation is the Fast Lightweight Peripheral Processor (FLPR), optimized to implement coprocessor functions, and operating at the same frequency as the application processor.

VPR is compatible with the RISC-V instruction set and implements the following extensions:

E – Integer instruction set with 16 registers
M – Multiply and divide extension
C – Compressed extension (compressed instructions)

VPR implements the machine mode CPU mode as well as the RISC-V CLIC specification for the interrupt controller.

VPR does not start on its own, but must be started by the application core processor by performing the following steps:

Configure VPR program counter (PC) to point to the peripheral binary image by using register INITPC.
Start VPR by using register CPURUN.

VPR registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
VPR00 : S VPR00 : NS	GLOBAL	0x5004C000 0x4004C000	US	NS	NA	No	FLPR - VPR peripheral registers

Configuration


Instance	Domain	Configuration
VPR00 : S VPR00 : NS	GLOBAL	VEVIF indexes 16 through 19 maps onto DPPI channels 0 through 4 Supports RV32E (Base Integer Instruction Set embedded) Supports M extension (Integer Multiplication and Division) Supports C extension (compressed instructions) Supports Zba extension (Bit Manipulation - Address generation instructions) Supports Zbb extension (Bit Manipulation - Basic bit manipulation) Supports Zbc extension (Bit Manipulation - Carry-less multiplication) Supports Zbs extension (Bit Manipulation - Single bit instructions) Supports Zcb extension (code-size saving instructions) Does not support FENCE.I instruction (use FENCE instruction instead) Supports CSR (Control and Status Register) instructions Does not support CNTR (base counter) instructions Supports M-mode CLIC (interrupt controller) Supports MCLICCFG register Supports external debugger Debugger supports triggers (breakpoints) Boot vector (INIT_PC_RESET_VALUE): 0x00000000 Self-booting (VPR_START_RESET_VALUE): 0 VPR RAM base address (RAM_BASE_ADDR): 0x20000000 VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM size)) Retain registers in Deep Sleep mode: 0 Restore VPR context at VPR reset using register [NRF_MEMCONF->POWER1.RET].MEM[0] VPR context save address: 0x2002FD40 VPR context save size: 512 bytes VPR remap address: 0x00000000 VEVIF tasks: 16..22 Mask of supported VEVIF tasks: 0x007F0000 VEVIF DPPI indices: 16..19 Mask of supported VEVIF DPPI channels: 0x000F0000 VEVIF events: 16..22 Mask of supported VEVIF events: 0x00100000 Debugger interface register offset: 0x5004C400 New RTP features

Register overview


Register	Offset	Description
TASKS_TRIGGER[n]	0x000	VPR task [n] register
SUBSCRIBE_TRIGGER[n]	0x080	Subscribe configuration for task TASKS_TRIGGER[n]
EVENTS_TRIGGERED[n]	0x100	VPR event [n] register
PUBLISH_TRIGGERED[n]	0x180	Publish configuration for event EVENTS_TRIGGERED[n]
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
INTPEND	0x30C	Pending interrupts
DEBUGIF.DATA0	0x410	Abstract Data 0. Read/write data for argument 0
DEBUGIF.DATA1	0x414	Abstract Data 1. Read/write data for argument 1
DEBUGIF.DMCONTROL	0x440	Debug Module Control
DEBUGIF.DMSTATUS	0x444	Debug Module Status
DEBUGIF.HARTINFO	0x448	Hart Information
DEBUGIF.HALTSUM1	0x44C	Halt Summary 1
DEBUGIF.HAWINDOWSEL	0x450	Hart Array Window Select
DEBUGIF.HAWINDOW	0x454	Hart Array Window
DEBUGIF.ABSTRACTCS	0x458	Abstract Control and Status
DEBUGIF.ABSTRACTCMD	0x45C	Abstract command
DEBUGIF.ABSTRACTAUTO	0x460	Abstract Command Autoexec
DEBUGIF.CONFSTRPTR[n]	0x464	Configuration String Pointer [n]
DEBUGIF.NEXTDM	0x474	Next Debug Module
DEBUGIF.PROGBUF[n]	0x480	Program Buffer [n]
DEBUGIF.AUTHDATA	0x4C0	Authentication Data
DEBUGIF.HALTSUM2	0x4D0	Halt Summary 2
DEBUGIF.HALTSUM3	0x4D4	Halt Summary 3
DEBUGIF.SBADDRESS3	0x4DC	System Bus Addres 127:96
DEBUGIF.SBCS	0x4E0	System Bus Access Control and Status
DEBUGIF.SBADDRESS0	0x4E4	System Bus Addres 31:0
DEBUGIF.SBADDRESS1	0x4E8	System Bus Addres 63:32
DEBUGIF.SBADDRESS2	0x4EC	System Bus Addres 95:64
DEBUGIF.SBDATA0	0x4F0	System Bus Data 31:0
DEBUGIF.SBDATA1	0x4F4	System Bus Data 63:32
DEBUGIF.SBDATA2	0x4F8	System Bus Data 95:64
DEBUGIF.SBDATA3	0x4FC	System Bus Data 127:96
DEBUGIF.HALTSUM0	0x500	Halt summary 0
CPURUN	0x800	State of the CPU after a core reset
VPRSTATUS	0x804	VPR state information.
INITPC	0x808	Initial value of the PC at CPU start.

TASKS_TRIGGER[n]

Address offset: 0x000 + (n × 0x4)

VPR task [n] register

If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally

If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_TRIGGER										VPR task [n] register If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).
			Trigger	1								Trigger task

Address offset: 0x080 + (n × 0x4)

Subscribe configuration for task TASKS_TRIGGER[n]

If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally

If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CHIDX										DPPI channel that task TASKS_TRIGGER[n] will subscribe to
B	RW	EN										Subscription enable bit
			Disabled	0x0								Disable subscription
			Enabled	0x1								Enable subscription

EVENTS_TRIGGERED[n]

Address offset: 0x100 + (n × 0x4)

VPR event [n] register

If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally

If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_TRIGGERED										VPR event [n] register If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).
			NotGenerated	0								Event not generated
			Generated	1								Event generated

PUBLISH_TRIGGERED[n]

Address offset: 0x180 + (n × 0x4)

Publish configuration for event EVENTS_TRIGGERED[n]

If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally

If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CHIDX										DPPI channel that event EVENTS_TRIGGERED[n] will publish to
B	RW	EN										Publication enable bit
			Disabled	0x0								Disable publishing
			Enabled	0x1								Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID													G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
	RW	TRIGGERED[i] (i=16..22)										Enable or disable interrupt for event TRIGGERED[i] If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID													G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
	RW W1S	TRIGGERED[i] (i=16..22)										Write '1' to enable interrupt for event TRIGGERED[i] If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID													G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
	RW W1C	TRIGGERED[i] (i=16..22)										Write '1' to disable interrupt for event TRIGGERED[i] If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTPEND

Address offset: 0x30C

Pending interrupts


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID													G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
	R	TRIGGERED[i] (i=16..22)										Read pending status of interrupt for event TRIGGERED[i] If RTPs are not enabled: writes to registers 15..0 are ignored, other read/write accesses operate normally If RTPs are enabled: reads or writes to these registers will be stalled if there is a simultaneous VPR CSR write access to any of the VEVIF CSR registers (except VEVENTSB and VEVENTSBS).
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending

DEBUGIF.DATA0

Address offset: 0x410

Abstract Data 0. Read/write data for argument 0


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DATA0										Abstract Data 0

DEBUGIF.DATA1

Address offset: 0x414

Abstract Data 1. Read/write data for argument 1


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DATA1										Abstract Data 1

DEBUGIF.DMCONTROL

Address offset: 0x440

Debug Module Control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				K	J	I	H		G	F	F	F	F	F	F	F	F	F	F	E	E	E	E	E	E	E	E	E	E			D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DMACTIVE										Reset signal for the debug module.
			Disabled	0								Reset the debug module itself
			Enabled	1								Normal operation
B	RW	NDMRESET										Reset signal output from the debug module to the system.
			Inactive	0								Reset inactive
			Active	1								Reset active
C	W	CLRRESETHALTREQ										Clear the halt on reset request.
			NoOperation	0								No operation when written 0.
			Clear	1								Clears the halt on reset request
D	W	SETRESETHALTREQ										Set the halt on reset request.
			NoOperation	0								No operation when written 0.
			Set	1								Sets the halt on reset request
E	W	HARTSELHI										The high 10 bits of hartsel.
F	W	HARTSELLO										The low 10 bits of hartsel.
G	W	HASEL										Definition of currently selected harts.
			Single	0								Single hart selected.
			Multiple	1								Multiple harts selected
H	W	ACKHAVERESET										Clear the havereset.
			NoOperation	0								No operation when written 0.
			Clear	1								Clears the havereset for selected harts.
I	RW	HARTRESET										Reset harts.
			Deasserted	0								Reset de-asserted.
			Asserted	1								Reset asserted.
J	W	RESUMEREQ										Resume currently selected harts.
			NoOperation	0								No operation when written 0.
			Resumed	1								Currently selected harts resumed.
K	W	HALTREQ										Halt currently selected harts.
			Clear	0								Clears halt request bit for all currently selected harts.
			Halt	1								Currently selected harts halted.

DEBUGIF.DMSTATUS

Address offset: 0x444

Debug Module Status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID													R			Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A	A	A	A
Reset 0x00400082				0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	VERSION										Version of the debug module.
			NotPresent	0								Debug module not present.
			V011	1								There is a Debug Module and it conforms to version 0.11 of this specifcation.
			V013	2								There is a Debug Module and it conforms to version 0.13 of this specifcation.
			NonConform	15								There is a Debug Module but it does not conform to any available version of the spec.
B	R	CONFSTRPTRVALID										Configuration string.
			NotRelevant	0								The confstrptr0..confstrptr3 holds information which is not relevant to the configuration string.
			Address	1								The confstrptr0..confstrptr3 holds the address of the configuration string.
C	R	HASRESETHALTREQ										Halt-on-reset support status.
			No	0								Halt-on-reset is supported.
			Yes	1								Halt-on-reset is not supported.
D	R	AUTHBUSY										Authentication busy status.
			No	0								The authentication module is ready.
			Yes	1								The authentication module is busy.
E	R	AUTHENTICATED										Authentication status.
			No	0								Authentication required before using the debug module.
			Yes	1								Authentication passed.
F	R	ANYHALTED										Any currently selected harts halted status.
			No	0								None of the currently selected harts halted.
			Yes	1								Any of the currently selected harts halted.
G	R	ALLHALTED										All currently selected harts halted status.
			No	0								Not all of the currently selected harts halted.
			Yes	1								All of the currently selected harts halted.
H	R	ANYRUNNING										Any currently selected harts running status.
			No	0								None of the currently selected harts running.
			Yes	1								Any of the currently selected harts running.
I	R	ALLRUNNING										All currently selected harts running status.
			No	0								Not all of the currently selected harts running.
			Yes	1								All of the currently selected harts running.
J	R	ANYUNAVAIL										Any currently selected harts unavailable status.
			No	0								None of the currently selected harts unavailable.
			Yes	1								Any of the currently selected harts unavailable.
K	R	ALLUNAVAIL										All currently selected harts unavailable status.
			No	0								Not all of the currently selected harts unavailable.
			Yes	1								All of the currently selected harts unavailable.
L	R	ANYNONEXISTENT										Any currently selected harts nonexistent status.
			No	0								None of the currently selected harts nonexistent.
			Yes	1								Any of the currently selected harts nonexistent.
M	R	ALLNONEXISTENT										All currently selected harts nonexistent status.
			No	0								Not all of the currently selected harts nonexistent.
			Yes	1								All of the currently selected harts nonexistent.
N	R	ANYRESUMEACK										Any currently selected harts acknowledged last resume request.
			No	0								None of the currently selected harts acknowledged last resume request.
			Yes	1								Any of the currently selected harts acknowledged last resume request.
O	R	ALLRESUMEACK										All currently selected harts acknowledged last resume
			No	0								Not all of the currently selected harts acknowledged last resume request.
			Yes	1								All of the currently selected harts acknowledged last resume request.
P	R	ANYHAVERESET										Any currently selected harts have been reset and reset is not acknowledged.
			No	0								None of the currently selected harts have been reset and reset is not acknowledget.
			Yes	1								Any of the currently selected harts have been reset and reset is not acknowledge.
Q	R	ALLHAVERESET										All currently selected harts have been reset and reset is not acknowledge
			No	0								Not all of the currently selected harts have been reset and reset is not acknowledge.
			Yes	1								All of the currently selected harts have been reset and reset is not acknowledge.
R	R	IMPEBREAK										Implicit ebreak instruction at the non-existent word immediately after the Program Buffer.
			No	0								No implicit ebreak instruction.
			Yes	1								Implicit ebreak instruction.

DEBUGIF.HARTINFO

Address offset: 0x448

Hart Information

This register gives information about the hart currently selected by hartsel. This register is optional. If it is not present it should read all-zero. If this register is included, the debugger can do more with the Program Buffer by writing programs which explicitly access the data and/or dscratch registers


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												D	D	D	D				C	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATAADDR		-2048 .. 2047								Data Address If dataaccess is 0: The number of the first CSR dedicated to shadowing the data registers. If dataaccess is 1: Address of RAM where the data registers are shadowed. This address is sign extended and easily addressed with a load or store using x0 as the address register.
B	R	DATASIZE		0 .. 12								Data Size If dataaccess is 0: Number of CSRs dedicated to shadowing the data registers. If dataaccess is 1: Number of 32-bit words in the memory map dedicated to shadowing the data registers. Since there are at most 12 data registers, the value in this register must be 12 or smaller
C	R	DATAACCESS										Data Access
			No	0								The data registers are shadowed in the hart by CSRs. Each CSR is DXLEN bits in size, and corresponds to a single argument.
			Yes	1								The data registers are shadowed in the hart’s memory map. Each register takes up 4 bytes in the memory map.
D	R	NSCRATCH										Number of dscratch registers Number of dscratch registers available for the debugger to use during program buffer execution, starting from dscratch0. The debugger can make no assumptions about the contents of these registers between commands.

DEBUGIF.HALTSUM1

Address offset: 0x44C

Halt Summary 1

Each bit in this read-only register indicates whether any of a group of harts is halted or not. Unavailable/nonexistent harts are not considered to be halted. This register might not be present if fewer than 33 harts are connected to this DM. The LSB reflects the halt status of harts hartsel[19:10] 0x0 through 0x1f. The MSB reflects the halt status of harts hartsel[19:10] 0x3e0 through 0x3ff.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HALTSUM1										Halt Summary 1

DEBUGIF.HAWINDOWSEL

Address offset: 0x450

Hart Array Window Select

This register selects which of the 32-bit portion of the hart array mask register is accessible in hawindow


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																					A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HAWINDOWSEL										The high bits of this field may be tied to 0, depending on how large the array mask register is. E.g. on a system with 48 harts only bit 0 of this field may actually be writable.

DEBUGIF.HAWINDOW

Address offset: 0x454

Hart Array Window

This register provides R/W access to a 32-bit portion of the hart array mask register. The position of the window is determined by hawindowsel. I.e. bit 0 refers to hart hawindowsel x 32, while bit 31 refers to hart hawindowsel x 32 + 31. Since some bits in the hart array mask register may be constant 0, some bits in this register may be constant 0, depending on the current value of hawindowsel.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MASKDATA										Mask data.

DEBUGIF.ABSTRACTCS

Address offset: 0x458

Abstract Control and Status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID							D	D	D	D	D												C		B	B	B					A	A	A	A
Reset 0x01000002				0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATACOUNT										Number of data registers that are implemented as part of the abstract command interface. Valid sizes are 1..12.
B	RW	CMDERR										Command error when the abstract command fails.
			NoError	0								No error.
			Busy	1								An abstract command was executing while command, abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read or written. This status is only written if cmderr contains 0
			NotSupported	2								The requested command is notsupported, regardless of whether the hart is running or not.
			Exception	3								An exception occurred while executing the command (e.g. while executing theProgram Buffer).
			HaltResume	4								The abstract command couldn't execute because the hart wasn't in the required state (running/halted). or unavailable.
			Bus	5								The abstract command failed due to abus error (e.g. alignment, access size, or timeout).
			Other	7								The command failed for another reason.
C	R	BUSY										Abstract command execution status.
			NotBusy	0								Not busy.
			Busy	1								An abstract command is currently being executed. This bit is set as soon as command is written, and is not cleared until that command has completed.
D	R	PROGBUFSIZE										Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1.

DEBUGIF.ABSTRACTCMD

Address offset: 0x45C

Abstract command


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	CONTROL										This Field is interpreted in a command specific manner, described for each abstract command.
B	W	CMDTYPE										The type determines the overall functionality of this abstract command.
			REGACCESS	0								Register Access Command
			MEMACCESS	2								Memory Access Command

DEBUGIF.ABSTRACTAUTO

Address offset: 0x460

Abstract Command Autoexec

This register is optional. Including it allows more efficient burst accesses. A debugger can detect whether it is support by setting bits and reading them back. Writing this register while an abstract command is executing causes cmderr to become 1 (busy) once the command completes (busy becomes 0).


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B					A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	AUTOEXECDATA										When a bit in this field is 1, read or write accesses to the corresponding data word cause the command in command to be executed again.
B	R	AUTOEXECPROGBUF										When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause the command in command to be executed again.

DEBUGIF.CONFSTRPTR[n]

Address offset: 0x464 + (n × 0x4)

Configuration String Pointer [n]

When confstrptrvalid is set, reading this register returns bits 31:0 of the configuration string pointer. Reading the other confstrptr registers returns the upper bits of the address. When system bus mastering is implemented, this must be an address that can be used with the System Bus Access module. Otherwise, this must be an address that can be used to access the configuration string from the hart with ID 0.32 RISC-V External Debug Support Version 0.13.2 If confstrptrvalid is 0, then the confstrptr registers hold identifier information.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ADDR										Address

DEBUGIF.NEXTDM

Address offset: 0x474

Next Debug Module

If there is more than one DM accessible on this DMI, this register contains the base address of the next one in the chain, or 0 if this is the last one in the chain.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ADDR										Address

DEBUGIF.PROGBUF[n]

Address offset: 0x480 + (n × 0x4)

Program Buffer [n]

progbuf0 through progbuf15 provide read/write access to the optional program buffer. progbufsize indicates how many of them are implemented starting at progbuf0, counting up. Accessing these registers while an abstract command is executing causes cmderr to be set to 1 (busy) if it is 0. Attempts to write them while busy is set does not change their value. The values in these registers may not be preserved after an abstract command is executed. The only guarantees on their contents are the ones offered by the command in question. If the command fails, no assumptions can be made about the contents of these registers.

Note: The VPR implements a single progbuf, all others (beyond progbuf0) are hardwired 0


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DATA										Data

DEBUGIF.AUTHDATA

Address offset: 0x4C0

Authentication Data

This register serves as a 32-bit serial port to/from the authentication module. When authbusy is clear, the debugger can communicate with the authentication module by reading or writing this register. There is no separate mechanism to signal overflow/underflow.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATA										Data

DEBUGIF.HALTSUM2

Address offset: 0x4D0

Halt Summary 2

Each bit in this read-only register indicates whether any of a group of harts is halted or not. Unavailable/nonexistent harts are not considered to be halted. This register might not be present if fewer than 1025 harts are connected to this DM. The LSB reflects the halt status of harts hartsel[19:15] 0x0 through hartsel[19:15] 0x3ff. The MSB reflects the halt status of harts hartsel[19:15] 0x7c00 through hartsel[19:15] 0x7fff


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HALTSUM2										Halt Summary 2

DEBUGIF.HALTSUM3

Address offset: 0x4D4

Halt Summary 3

Each bit in this read-only register indicates whether any of a group of harts is halted or not. Unavailable/nonexistent harts are not considered to be halted. This register might not be present if fewer than 32769 harts are connected to this DM. The LSB reflects the halt status of harts 0x0 through 0x7fff. The MSB reflects the halt status of harts 0xf8000 through 0xfffff


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HALTSUM3										Halt Summary 3

DEBUGIF.SBADDRESS3

Address offset: 0x4DC

System Bus Addres 127:96

If sbasize is less than 97, then this register is not present. When the system bus master is busy, writes to this register will set sbbusyerror and don’t do anything else.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ADDRESS										Accesses bits 127:96 of the physical address in sbaddress (if the system address bus is that wide).

DEBUGIF.SBCS

Address offset: 0x4E0

System Bus Access Control and Status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				N	N	N							M	L	K	J	J	J	I	H	G	G	G	F	F	F	F	F	F	F	E	D	C	B	A
Reset 0x20000000				0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	SBACCESS8										8-bit system bus accesses are supported.
B	R	SBACCESS16										16-bit system bus accesses are supported.
C	R	SBACCESS32										32-bit system bus accesses are supported.
D	R	SBACCESS64										64-bit system bus accesses are supported.
E	R	SBACCESS128										128-bit system bus accesses are supported.
F	R	SBASIZE										Width of system bus addresses in bits. (0 indicates there is no bus access support.)
G	R	SBERROR										When the Debug Module’s system bus master encounters an error, this field gets set. The bits in this field remain set until they are cleared by writing 1 to them. While this field is non-zero, no more system bus accesses can be initiated by the Debug Module. An implementation may report Other error (7) for any error condition.
			Normal	0								There was no bus error.
			Timeout	1								There was a timeout.
			Address	2								A bad address was accessed.
			Alignment	3								There was an alignment error.
			Size	4								An access of unsupported size was requested.
			Other	7								Other.
H	R	SBREADONDATA
			sbreadondata	1								Every read from sbdata0 automatically triggers a system bus read at the (possibly autoincremented) address.
I	R	SBAUTOINCREMENT
			sbautoincrement	1								sbaddress is incremented by the access size (in bytes) selected in sbaccess after every system bus access.
J	R	SBACCESS										Select the access size to use for system bus accesses. If sbaccess has an unsupported value when the DM starts a bus access, the access is not performed and sberror is set to 4.
			size8	0								8-bit.
			size16	1								16-bit.
			size32	2								32-bit.
			size64	3								64-bit.
			size128	4								128-bit.
K	R	SBREADONADDR
			sbreadonaddr	1								Every write to sbaddress0 automatically triggers a system bus read at the new address.
L	R	SBBUSY										(Whether the system bus itself is busy is related, but not the same thing.) This bit goes high immediately when a read or write is requested for any reason, and does not go low until the access is fully completed. Writes to sbcs while sbbusy is high result in undefined behavior. A debugger must not write to sbcs until it reads sbbusy as 0.
			notbusy	0								System bus master is not busy.
			busy	1								System bus master is busy.
M	R	SBBUSYERROR										Set when the debugger attempts to read data while a read is in progress, or when the debugger initiates a new access while one is already in progress (while sbbusy is set). It remains set until it’s explicitly cleared by the debugger. While this field is set, no more system bus accesses can be initiated by the Debug Module.
			noerror	0								No error.
			error	1								Debugger access attempted while one in progress.
N	R	SBVERSION
			version0	0								The System Bus interface conforms to mainline drafts of thia RISC-V External Debug Support spec older than 1 January, 2018.
			version1	1								The System Bus interface conforms to RISC-V External Debug Support version 0.13.2. Other values are reserved for future versions.

DEBUGIF.SBADDRESS0

Address offset: 0x4E4

System Bus Addres 31:0

If sbasize is 0, then this register is not present. When the system bus master is busy, writes to this register will set sbbusyerror and don’t do anything else. If sberror is 0, sbbusyerror is 0, and sbreadonaddr is set then writes to this register start the following: 1. Set sbbusy. 2. Perform a bus read from the new value of sbaddress. 3. If the read succeeded and sbautoincrement is set, increment sbaddress. 4. Clear sbbusy.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ADDRESS										Accesses bits 31:0 of the physical address in sbaddress.

DEBUGIF.SBADDRESS1

Address offset: 0x4E8

System Bus Addres 63:32

If sbasize is less than 33, then this register is not present. When the system bus master is busy, writes to this register will set sbbusyerror and don’t do anything else.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ADDRESS										Accesses bits 63:32 of the physical address in sbaddress (if the system address bus is that wide).

DEBUGIF.SBADDRESS2

Address offset: 0x4EC

System Bus Addres 95:64

If sbasize is less than 65, then this register is not present. When the system bus master is busy, writes to this register will set sbbusyerror and don’t do anything else.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	ADDRESS										Accesses bits 95:64 of the physical address in sbaddress (if the system address bus is that wide).

DEBUGIF.SBDATA0

Address offset: 0x4F0

System Bus Data 31:0

If all of the sbaccess bits in sbcs are 0, then this register is not present. Any successful system bus read updates sbdata. If the width of the read access is less than the width of sbdata, the contents of the remaining high bits may take on any value. If either sberror or sbbusyerror isn’t 0 then accesses do nothing. If the bus master is busy then accesses set sbbusyerror, and don’t do anything else. Writes to this register start the following: 1. Set sbbusy. 2. Perform a bus write of the new value of sbdata to sbaddress. 3. If the write succeeded and sbautoincrement is set, increment sbaddress. 4. Clear sbbusy. Reads from this register start the following: 1. “Return” the data. 2. Set sbbusy. 3. If sbreadondata is set: (a) Perform a system bus read from the address contained in sbaddress, placing the result in sbdata. (b) If sbautoincrement is set and the read was successful, increment sbaddress. 4. Clear sbbusy. Only sbdata0 has this behavior. The other sbdata registers have no side effects. On systems that have buses wider than 32 bits, a debugger should access sbdata0 after accessing the other sbdata registers


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATA										Accesses bits 31:0 of sbdata

DEBUGIF.SBDATA1

Address offset: 0x4F4

System Bus Data 63:32

If sbaccess64 and sbaccess128 are 0, then this register is not present. If the bus master is busy then accesses set sbbusyerror, and don’t do anything else.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATA										Accesses bits 63:32 of sbdata (if the system bus is that wide).

DEBUGIF.SBDATA2

Address offset: 0x4F8

System Bus Data 95:64

This register only exists if sbaccess128 is 1. If the bus master is busy then accesses set sbbusyerror, and don’t do anything else


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATA										Accesses bits 95:64 of sbdata (if the system bus is that wide).

DEBUGIF.SBDATA3

Address offset: 0x4FC

System Bus Data 127:96

This register only exists if sbaccess128 is 1. If the bus master is busy then accesses set sbbusyerror, and don’t do anything else


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DATA										Accesses bits 127:96 of sbdata (if the system bus is that wide).

DEBUGIF.HALTSUM0

Address offset: 0x500

Halt summary 0

Each bit in this read-only register indicates whether one specific hart is halted or not. Unavailable/nonexistent harts are not considered to be halted. This register might not be present if fewer than 2 harts are connected to this DM. The LSB reflects the halt status of hart hartsel[19:5] 0x0, and the MSB reflects halt status of hart hartsel[19:5] 0xf


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HALTSUM0										Halt summary 0

CPURUN

Address offset: 0x800

State of the CPU after a core reset


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EN										Controls CPU running state after a core reset.
			Stopped	0								CPU stopped. If this is the CPU state after a core reset, setting this bit will change the CPU state to CPU running.
			Running	1								CPU running. If this is the CPU state after a core reset, clearing this bit will change the CPU state to CPU stopped after a core reset.

VPRSTATUS

Address offset: 0x804

VPR state information.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														C	B	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CPUSTATUS										Enumerates one of several possible states for the VPR:
			WAITING	0x0								WAITING (not yet started)
			RUNNING	0x1								RUNNING
			SLEEPING	0x2								SLEEPING
			INTERRUPT	0x3								INTERRUPT (in handler)
			EXCEPTION_TRAP	0x4								EXCEPTION/TRAP (in handler)
			ONGOING_RESET	0x5								ONGOING_RESET
			HALTED	0x6								HALTED
			ERROR	0xE								ERROR (lockup, needs debugging or reset)
B	R	RTPENABLED										Mirrors the ENABLERTPERIPH bit in the NORDIC.VPRNORDICCTRL CSR When this bit is cleared, it will override the APB read value of the INTEN register to 0.
			Disabled	0								Real-time peripherals disabled
			Enabled	1								Real-time peripherals enabled
C	R	RTPSTALL										Stalled waiting for real-time peripheral blocking CSR access, for example WAIT, OUTB with dirty status
			NotStalled	0								CPU not stalled on blocing CSR access.
			Stalled	1								CPU stalled on blocing CSR access.

INITPC

Address offset: 0x808

Initial value of the PC at CPU start.

Note: This address must be 64 bit aligned


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	INITPC										Initial value of the PC at CPU start. This value should be set before setting CPURUN.EN. After setting CPURUN.EN, this register can be reconfigured to prepare the CPU to start from a new initial PC upon receiving a reset request Note: This value is used directly, so take care if changing it after VPR has started. Temporarily disabling interrupts is recommended if you need to update it. The bottom 2 bits are ignored.

VPR CLIC registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
VPRCLIC	FLPR	0xF0000000	HF	NS	NA	No	VPR CLIC registers

Configuration


Instance	Domain	Configuration
VPRCLIC	FLPR	Supported interrupts (IRQNUM): 0..270 VEVIF tasks: 0..31 Mask of supported VEVIF tasks: 0xFFFFFFFF VPR counter (CNT0) interrupt handler number (COUNTER_IRQ_NUM): 31 CLIC supports 2 level bits

Register overview


Register	Offset	Description
CLIC.CLICCFG	0x0000	CLIC configuration.
CLIC.CLICINFO	0x0004	CLIC information.
CLIC.CLICINT[n]	0x1000	Interrupt control register for IRQ number [n].

CLIC.CLICCFG

Address offset: 0x0000

CLIC configuration.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													C	C	B	B	B	B	A
Reset 0x00000011				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	R	NVBITS										Selective interrupt hardware vectoring.
			Implemented	1								Selective interrupt hardware vectoring is implemented
B	R	NLBITS										Interrupt level encoding. Indicates how many upper bits are assigned to encode the interrupt level in CLICINT[n].PRIORITY
			Eight	8								8 bits = interrupt levels encoded in eight bits
C	R	NMBITS										Interrupt privilege mode. Indicates how many bits represent privilege mode
			ModeM	0								All interrupts are M-mode only

CLIC.CLICINFO

Address offset: 0x0004

CLIC information.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					C	C	C	C	C	C					B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00401FFF				0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	NUMINTERRUPTS										Maximum number of interrupts supported.
B	R	VERSION										Version
C	R	NUMTRIGGER										Number of maximum interrupt triggers supported

CLIC.CLICINT[n]

Address offset: 0x1000 + (n × 0x4)

Interrupt control register for IRQ number [n].


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				H	H	H	H	H	H	H	H	G	G				F	F	E	D	D	D	D	D	D	D	C	B	B	B	B	B	B	B	A
Reset 0x3FC30000				0	0	1	1	1	1	1	1	1	1	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	IP										Interrupt Pending bit.
			NotPending	0								Interrupt not pending
			Pending	1								Interrupt pending
B	R	READ1										Read as 0, write ignored.
C	RW	IE										Interrupt enable bit.
			Disabled	0								Interrupt disabled
			Enabled	1								Interrupt enabled
D	R	READ2										Read as 0, write ignored.
E	R	SHV										Selective Hardware Vectoring.
			Vectored	1								Hardware vectored
F	R	TRIG										Trigger type and polarity for each interrupt input.
			EdgeTriggered	1								Interrupts are edge-triggered
G	R	MODE										Privilege mode.
			MachineMode	3								Machine mode
H	RW	PRIORITY										Interrupt priority level
			PRIO3F	0x3F								Priority level 0x3F
			PRIO7F	0x7F								Priority level 0x7F
			PRIOBF	0xBF								Priority level 0xBF
			PRIOFF	0xFF								Priority level 0xFF
			PRIOLEVEL0	0x3F								Priority level 0 This enumerator is deprecated.
			PRIOLEVEL1	0x7F								Priority level 1 This enumerator is deprecated.
			PRIOLEVEL2	0xBF								Priority level 2 This enumerator is deprecated.
			PRIOLEVEL3	0xFF								Priority level 3 This enumerator is deprecated.

VPR Control Status Registers (CSRs)

Instances


Instance	Domain	Base address	Description
VPRCSR	FLPR		VPR CSR registers

Configuration


Instance	Domain	Configuration
VPRCSR	FLPR	VEVIF indexes 16 through 19 maps onto DPPI channels 0 through 4 Use GPIO port P1 HARTNUM: 14 MCLICBASE: 0xF0000000 HIBERNATE: 1 DBG: 1 Number of HW breakpoints: 1 VPR cannot be retained CSR VIOPINS value: 0x000003FF VEVIF tasks: 0..31 Mask of supported VEVIF tasks: 0xFFFFFFFF VEVIF DPPI indices: 16..19 VEVIF events: 0..31 CACHE available OUTMODE for shifting functionality available VPR does not support peripheral blocking access New RTP features CLIC supports 2 level bits

Register overview


Register	Offset	Description
MSTATUS	0x300	Machine Status
MISA	0x301	Machine ISA
MTVEC	0x305	Machine Trap-Vector
MTVT	0x307	Machine Trap Vector Table
MCOUNTINHIBIT	0x320	Machine Counter-Inhibit
MSCRATCH	0x340	Machine Scratch
MEPC	0x341	Machine Exception Program Counter
MCAUSE	0x342	Machine Cause
MTVAL	0x343	Machine Trap Value
MINTSTATUS	0x346	M-mode Interrupt Status
MINTTHRESH	0x347	M-mode Interrupt-level Threshold
MCLICBASE	0x350	Machine CLIC Base
TSELECT	0x7A0	Trigger Select
TDATA1	0x7A1	Trigger Data 1
TDATA2	0x7A2	Trigger Data 2
TDATA3	0x7A3	Trigger Data 3
TINFO	0x7A4	Trigger Info
TCONTROL	0x7A5	Trigger Control
DCSR	0x7B0	Debug Control and Status
DPC	0x7B1	Debug PC
MCYCLE	0xB00	Machine Cycle Counter
MINSTRET	0xB02	Machine Instruction Counter
MCYCLEH	0xB80	Machine Cycle Counter (Upper part)
MINSTRETH	0xB82	Machine Instruction Counter (Upper part)
UCYCLE	0xC00	User Cycle Counter
UINSTRET	0xC02	User Instruction Counter
UCYCLEH	0xC80	User Cycle Counter (Upper part)
UINSTRETH	0xC82	User Instruction Counter (Upper part)
MVENDORID	0xF11	Machine Vendor ID
MARCHID	0xF12	Machine Architecture ID
MIMPID	0xF13	Machine Implementation ID
MHARTID	0xF14	Machine Hart ID
NORDIC.VPRNORDICCTRL	0x7C0	Nordic Core Control
NORDIC.VPRNORDICSLEEPCTRL	0x7C1	Nordic Sleep Control
NORDIC.VPRNORDICFEATURESDISABLE	0x7C2	Contains disable bits for certain features in the core
NORDIC.VIOPINS	0x7C3	VPR pins used for Real Time Peripherals VIO
NORDIC.EXTPARAMS	0x7C4	Reads values of external configuration parameters
NORDIC.AXCACHE	0x7C5	Memory type encoding
NORDIC.CACHE.CTRL	0x7C8	Cache control
NORDIC.CACHE.CFG	0x7C9	Cache configuration
NORDIC.CACHE.DATATAGADDR	0x7CA	Cache tag base address
NORDIC.CACHE.DATABASEADDR	0x7CB	Cache data base address
NORDIC.RTPERIPHCTRL	0x7CC	RT peripheral control
NORDIC.RTPERIPHSTATUS	0x7CD	Real-Time Peripheral Status
NORDIC.CNTMODE0	0x7D0	CNT0 Mode
NORDIC.CNTMODE1	0x7D1	CNT1 Mode
NORDIC.CNT	0x7D2	32-bit Counter
NORDIC.CNTTOP	0x7D3	Counter Top
NORDIC.CNTADD	0x7D4	CNT Add
NORDIC.CNT0	0x7D5	16-bit Counter 0
NORDIC.CNTADD0	0x7D6	CNT0 Add
NORDIC.CNT1	0x7D7	16-bit Counter 1
NORDIC.CNTADD1	0x7D8	CNT1 Add
NORDIC.WAIT0	0x7DA	Wait 0
NORDIC.WAIT1	0x7DB	Wait 1
NORDIC.WAIT	0x7DC	Wait
NORDIC.TASKS	0x7E0	DPPI Tasks
NORDIC.SUBSCRIBE	0x7E1	Enable Task Subscription
NORDIC.EVENTS	0x7E2	DPPI Events
NORDIC.PUBLISH	0x7E3	Enable Event Publication
NORDIC.INTEN	0x7E4	DPPI Event Interrupt Enable
NORDIC.EVENTSB	0x7E5	Buffered DPPI Events
NORDIC.EVENTSBS	0x7E6	EVENTSB Dirty Status
NORDIC.OUT	0xBC0	GPIO Output value. Real Time Peripherals VIO.
NORDIC.DIR	0xBC1	GPIO pin Direction. Real Time Peripherals VIO.
NORDIC.IN	0xBC2	GPIO Input. Real Time Peripherals VIO.
NORDIC.INMODE	0xBC3	Input Mode
NORDIC.OUTB	0xBC4	Buffered GPIO Output
NORDIC.DIRB	0xBC5	Buffered GPIO pin Direction
NORDIC.DIROUT	0xBC6	DIR and OUT concatenation
NORDIC.DIROUTB	0xBC7	Concatenation of DIRB and OUTB
NORDIC.OUTBRB	0xBC8	Byte reversed register OUTB
NORDIC.OUTBRW	0xBC9	Word reversed register OUTB
NORDIC.INBRB	0xBCA	Byte reversed register INB
NORDIC.SHIFTCTRLB	0xBCB	Buffered IO shift control
NORDIC.SHIFTCNTIN	0xBCD	Number of frames to be shifted from INB before new data is required
NORDIC.SHIFTCNTOUT	0xBCE	Number of frames to be shifted to OUTB before new data is required
NORDIC.SHIFTCNTB	0xBCF	Buffered SHIFTCNTOUT and SHIFTCNTIN register
NORDIC.OUTTGL	0xBD0	GPIO Output Toggle
NORDIC.DIRTGL	0xBD1	GPIO pin Direction Toggle
NORDIC.OUTBTGL	0xBD2	Buffered GPIO Output Toggle
NORDIC.DIRBTGL	0xBD3	Buffered GPIO pin Direction Toggle
NORDIC.DIROUTTGL	0xBD4	DIROUT Toggle
NORDIC.DIROUTBTGL	0xBD5	DIROUTB Toggle
NORDIC.OUTUBTGL	0xBD6	Buffered GPIO Unshifted Output Toggle
NORDIC.OUTBS	0xBD8	Buffered GPIO Output Dirty Status
NORDIC.DIRBS	0xBD9	Buffered GPIO pin Direction Dirty Status
NORDIC.DIROUTBS	0xBDA	Combination of DIRB and OUTB Dirty Status
NORDIC.OUTUBS	0xBDB	Buffered GPIO Unshifted Output Dirty Status
NORDIC.OUTMODE	0xBE3	Serial output mode
NORDIC.OUTMODEB	0xBE4	Buffered OUTMODE register
NORDIC.INMODEB	0xBE5	Buffered INMODE register
NORDIC.INB	0xBE6	Buffered GPIO input
NORDIC.OUTUB	0xBE7	Buffered write to Unshifted parts of OUT
NORDIC.SHIFTCNTCOMP	0xBE8	SHIFTCNTIN/OUT compare values
NORDIC.WAITEVENT	0xBE9	Wait for internal event
NORDIC.WAITINPUT	0xBEA	Wait input
NORDIC.RTPINTEN	0xBEB	Interrupt enable
NORDIC.OUTUBTRIG	0xBEC	OUTUB trigger select

MSTATUS

Address offset: 0x300

Machine Status

Keeps track of and controls the hart current operating state. In VPR it only contains/controls information of machine privileged mode interrupts, see MIE and MPIE


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																							C	C				B				A
Reset 0x00001800				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MIE										Global interrupt enable for machine privilege mode
			Disabled	0
			Enabled	1
B	RW	MPIE										Exists to support nested traps. Value of the interrupt-enable bit active prior to the trap for machine privilege mode
			Disabled	0
			Enabled	1
C	R	MPP										Exists to support nested traps. Value of the privlege mode prior to the trap for machine privilege mode

MISA

Address offset: 0x301

Machine ISA

Reports the ISA supported by the hart


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				I	I							H										G	F				E				D		C	B	A
Reset 0x40001016				0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	1	0	1	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	A										Atomic extension Indicates presence of standard A extension
			Disabled	0
			Enabled	1
B	R	B										Bit-Manipulation extension Indicates presence of standard B extension
			Disabled	0
			Enabled	1
C	R	C										Compressed extension Indicates presence of standard C extension
			Disabled	0
			Enabled	1
D	R	E										RV32E/RV64E base ISA Indicates presence of standard E extension
			Disabled	0
			Enabled	1
E	R	I										RV32I/64I/128I base ISA Indicates presence of standard I extension
			Disabled	0
			Enabled	1
F	R	M										Integer Multiply/Divide extension Indicates presence of standard M extension
			Disabled	0
			Enabled	1
G	R	N										User-level interrupts supported Indicates presence of standard N extension
			Disabled	0
			Enabled	1
H	R	X										Non-standard extensions present Indicates presence of standard non-standard extensions
			NotPresent	0
			Present	1
I	R	MXL										Machine XLEN Encodes the native base integer ISA width. The MXL field may be writable in implementations that support multiple base ISA widths. The effective XLEN in M-mode, MXLEN, is given by the setting of MXL, or has a fixed value if misa is zero. The MXL field is always set to the widest supported ISA variant at reset
			XLEN32	1								XLEN is 32 bits
			XLEN64	2								XLEN is 64 bits
			XLEN128	3								XLEN is 128 bits

MTVEC

Address offset: 0x305

Machine Trap-Vector

Holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A
Reset 0x00000003				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	MODE										Mode
			CLIC	3								Core Local Interrupt Controller (CLIC) interrupt handling mode
B	RW	BASE										Vector base address The BASE field value must align on an 8-byte boundary

MTVT

Address offset: 0x307

Machine Trap Vector Table

Holds the base address of the trap vector table, aligned on a 64-byte or greater power-of-two boundary. The actual alignment can be determined by writing ones to the low-order bits then reading them back.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Machine Trap Vector Table base address value for CLIC vectored interrupts

MCOUNTINHIBIT

Address offset: 0x320

Machine Counter-Inhibit


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	B		A
Reset 0x00000005				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	CY
			INCREMENT	0x0								MCYCLE increments as usual
			INHIBIT	0x1								MCYCLE doesn’t increment
B	RW	IR
			INCREMENT	0x0								MINSTRET increments as usual
			INHIBIT	0x1								MINSTRET doesn’t increment

MSCRATCH

Address offset: 0x340

Machine Scratch

Register dedicated for use by machine mode. Typically, it is used to hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Machine Scratch value

MEPC

Address offset: 0x341

Machine Exception Program Counter

When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mepc is never written by the implementation, though it may be explicitly written by software


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Machine Exception Program Counter value

MCAUSE

Address offset: 0x342

Machine Cause

When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. Otherwise, mcause is never written by the implementation, though it may be explicitly written by software.

Note: Writing this register can have side effects, so care needs to be taken when initializing this for a new thread context. To be safe, initialize this to the reset value when creating a new thread.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				F	E	D	D	C				B	B	B	B	B	B	B	B					A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x30000000				0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EXCEPTIONCODE										Exception code See RISC-V Instruction Set Manual Volume II: Privileged Architecture for details on the exception codes. Exception codes listed here only apply if the trap is not caused by an interrupt (Interrupt bitfield set to 0)
			INSTADDRMISALIGN	0x0								Instruction Address Misaligned
			INSTACCESSFAULT	0x1								Instruction Access Fault
			ILLEGALINST	0x2								Illegal Instruction
			BKPT	0x3								Breakpoint
			LOADADDRMISALIGN	0x4								Load Address Misaligned
			LOADACCESSFAULT	0x5								Load Access Fault
			STOREADDRMISALIGN	0x6								Store/AMO Address Misaligned
			STOREACCESSFAULT	0x7								Store/AMO Access Fault
			ECALLMMODE	0xB								Environment Call M-Mode
			MISALIGNSTACKING	0x18								Misaligned Stacking
			BUSFAULTSTACKING	0x19								Bus Fault on Stacking
			INTVECTORFAULT	0x1A								Interrupt Vector Fault
			MISALIGNUNSTACKING	0x1B								Misaligned Unstacking
			BUSFAULTUNSTACKING	0x1C								Bus Fault on Unstacking
			STORETIMEOUTFAULT	0x1D								Store Timeout Fault
			LOADTIMEOUTFAULT	0x1E								Load Timeout Fault
			STACKINGEXCFAULT	0x1F								Fault on Exception Stacking
B	RW	MPIL										Previous interrupt level
C	RW	MPIE										Previous interrupt enable, same as MSTATUS.MPIE
D	R	MPP										Previous privilege mode, same as MSTATUS.MPP
E	RW	MINHV										In hardware vectoring Set by hardware at start of hardware vectoring, cleared by hardware at end of successful hardware vectoring
F	RW	INTERRUPT										Interrupt bit Set if the trap was caused by an interrupt
			EXCEPTION	0
			INTERRUPT	1

MTVAL

Address offset: 0x343

Machine Trap Value

When a trap is taken into M-mode, MTVAL is either set to zero or written with exception-specific information to assist software in handling the trap. In VPR this register is ignored by exceptions and set to zero permanently


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VAL										Machine Trap Value

MINTSTATUS

Address offset: 0x346

M-mode Interrupt Status

Holds the active interrupt level for M-mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MIL										M-Mode interrupt level

MINTTHRESH

Address offset: 0x347

M-mode Interrupt-level Threshold

Holds an 8-bit field for the threshold level of M-mode. Typical use is to implement critical sections. The current hart’s effective interrupt level would then be: effective_level = max(MINTSTATUS.MIL, MINTTHRESH.TH)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x0000001F				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	TH										M-Mode Interrupt-level Threshold
			DISABLED	0x0								Threshold disabled Note: This can always be used to reset the threshold to the lowest supported level and let all interrupt levels through, even though it will not read back as this value afterwards.
			THRESH1F	0x1F								Threshold level 0x1F Note: This is the reset level, threshold disabled.
			THRESH3F	0x3F								Threshold level 0x3F
			THRESH7F	0x7F								Threshold level 0x7F
			THRESHBF	0xBF								Threshold level 0xBF
			THRESHFF	0xFF								Threshold level 0xFF
			THRESHLEVEL0	0x3F								Threshold level 0 This enumerator is deprecated.
			THRESHLEVEL1	0x7F								Threshold level 1 This enumerator is deprecated.
			THRESHLEVEL2	0xBF								Threshold level 2 This enumerator is deprecated.
			THRESHLEVEL3	0xFF								Threshold level 3 This enumerator is deprecated.

MCLICBASE

Address offset: 0x350

Machine CLIC Base

Provides the base address of CLIC memory mapped registers. Its value should be configured or set up at the platform level to indicate the starting address of CLIC memory mapped registers. Since the CLIC memory map must be aligned at a 4KiB boundary, the mclicbase CSR has its 12 least-significant bits hardwired to zero. It is used to inform software about the location of CLIC memory mappped registers.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xF0000000				1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VAL										CLIC base address value

TSELECT

Address offset: 0x7A0

Trigger Select

This register determines which trigger is accessible through the other trigger registers. The set of accessible triggers must start at 0, and be contiguous


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Trigger Select value

TDATA1

Address offset: 0x7A1

Trigger Data 1


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C	C	C	C	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DATA										Trigger Specific Data, refer to the RISC-V Debug Specification for more details.
B	RW	DMODE										Debug Mode This bit is only writable from Debug Mode
			BOTH	0								Both Debug and M-mode can write the tdata registers at the selected tselect.
			ONLYDEBUG	1								Only Debug Mode can write the tdata registers at the selected tselect. Writes from other modes are ignored.
C	RW	TYPE										Type
			NOTRIGGER	0x0								There is no trigger at this tselect
			MATCH	0x2								The trigger is an address match trigger. The remaining bits in this register act as described in mcontrol

TDATA2

Address offset: 0x7A2

Trigger Data 2


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DATA										Trigger Specific Data

TDATA3

Address offset: 0x7A3

Trigger Data 3


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DATA										Trigger Specific Data

TINFO

Address offset: 0x7A4

Trigger Info


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000004				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	INFO										Trigger Info value One bit for each possible type enumerated in tdata1. Bit N corresponds to type N. If the bit is set, then that type is supported by the currently selected trigger. If the currently selected trigger doesn’t exist, this field contains 1. If type is not writable, this register may be unimplemented, in which case reading it causes an illegal instruction exception. In this case the debugger can read the only supported type from tdata1.

TCONTROL

Address offset: 0x7A5

Trigger Control

This optional register is one solution to a problem regarding triggers with action=0 firing in M-mode trap handlers


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												B				A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MTE										Mode Trigger Enable
			DONTMATCH	0								Triggers with action=0 do not match/fire while the hart is in M-mode
			MATCH	1								Triggers do match/fire while the hart is in M-mode. When a trap into M-mode is taken, mte is set to 0. When mret is executed, mte is set to the value of mpte
B	R	MPTE										Mode Previous Trigger Enable When a trap into M-mode is taken, mpte is set to the value of mte

DCSR

Address offset: 0x7B0

Debug Control and Status

This register is only accesible from debug mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				F	F	F	F													E				D			C	C	C				B	A	A
Reset 0x40000003				0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	PRV										Privilege level Contains the privilege level the hart was operating in when Debug Mode was entered. VPR only supports Machine Privilege Level.
			MACHINE	3
B	RW	STEP										Step When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. The debugger must not change the value of this bit while the hart is running
C	R	CAUSE										Debug Mode enter cause When there are multiple reasons to enter Debug Mode in a single cycle, hardware should set cause to the cause with the highest priority. Values other than the following are reserved for future use
			EBREAK	1								An ebreak instruction was executed. (priority 3)
			TRIGGER	2								The Trigger Module caused a breakpoint exception. (priority 4, highest)
			HALTREQ	3								The debugger requested entry to Debug Mode using haltreq. (priority 1)
			STEP	4								The hart single stepped because step was set. (priority 0, lowest)
			RESETHALTREQ	5								The hart halted directly out of reset due to resethaltreq. It is also acceptable to report 3 when this happens. (priority 2)
D	RW	STEPIE										Step Interrupt Enable The debugger must not change the value of this bit while the hart is running
			Disabled	0								Interrupts are disabled during single stepping
			Enabled	1								Interrupts are enabled during single stepping. Implementations may hard wire this bit to 0. In that case interrupt behavior can be emulated by the debugger.
E	RW	EBREAKM										M-mode ebreak
			SPEC	0								ebreak instructions in M-mode behave as described in the Privileged Spe
			ENTERDBG	1								ebreak instructions in M-mode enter Debug Mode
F	R	XDEBUGVER										External Debug version
			STDDBG	4								External debug support exists as it is described in this document

DPC

Address offset: 0x7B1

Debug PC

Upon entry to debug mode, dpc is updated with the virtual address of the next instruction to be executed. When resuming, the hart’s PC is updated to the virtual address stored in dpc. A debugger may write dpc to change where the hart resumes


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Debug PC value

MCYCLE

Address offset: 0xB00

Machine Cycle Counter

Counts the number of clock cycles executed by the processor core on which the hart is running


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Machine Cycle Counter value

MINSTRET

Address offset: 0xB02

Machine Instruction Counter

Counts the number of instructions the hart has retired

In this context retired means a successfully executed instruction


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Machine Instruction Counter value

MCYCLEH

Address offset: 0xB80

Machine Cycle Counter (Upper part)

Counts the number of clock cycles executed by the processor core on which the hart is running


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Machine Cycle Counter value

MINSTRETH

Address offset: 0xB82

Machine Instruction Counter (Upper part)

Counts the number of instructions the hart has retired

In this context retired means a successfully executed instruction


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Machine Instruction Counter (Upper part) value

UCYCLE

Address offset: 0xC00

User Cycle Counter

Counts the number of clock cycles executed by the processor core on which the hart is running. This register is a read-only copy of MCYCLE


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VAL										User Cycle Counter value

UINSTRET

Address offset: 0xC02

User Instruction Counter

Counts the number of instructions the hart has retired. This register is a read-only copy of MINSTRET

In this context retired means a successfully executed instruction


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VAL										User Instruction Counter value

UCYCLEH

Address offset: 0xC80

User Cycle Counter (Upper part)

Counts the number of clock cycles executed by the processor core on which the hart is running. This register is a read-only copy of MCYCLEH


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VAL										User Cycle Counter value

UINSTRETH

Address offset: 0xC82

User Instruction Counter (Upper part)

Counts the number of instructions the hart has retired. This register is a read-only copy of MINSTRETH

In this context retired means a successfully executed instruction


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VAL										User Instruction Counter (Upper part) value

MVENDORID

Address offset: 0xF11

Machine Vendor ID

32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A
Reset 0x00000144				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	0	1	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	OFFSET										MVENDORID encodes the final byte in the Offset field, discarding the parity bit
B	R	BANK										MVENDORID encodes the number of one-byte continuation codes in the Bank field

MARCHID

Address offset: 0xF12

Machine Architecture ID

32-bit read-only register encoding the base microarchitecture of the hart


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				H																		G	G	G	F	E	E	E	E	D		C	B	A	A
Reset 0x8000006E				1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	MULDIV										Indicates the MULDIV parameter option
B	R	HIBERNATE										Indicates the POWEROFFSLEEP parameter option
C	R	DBG										Indicates the DBG parameter option
D	R	BUSWIDTH										Indicates the BUS_WIDTH parameter option
E	R	BKPT										Indicates the BKPT parameter option
F	R	CACHE										Indicates that the CACHE is present
G	R	CACHEEXTRATAGBUF										Indicates the number of extra TAG buffers in CACHE
H	R	IMPLEM										Indicates a non-open implementation

MIMPID

Address offset: 0xF13

Machine Implementation ID


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												C	C	C	C	C	C	C	C	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A
Reset 0x00010300				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	PATCHREV										Indicates the number of the patch revision
B	R	MINORREV										Indicates the number of the minor revision
C	R	MAJORREV										Indicates the number of the major revison

MHARTID

Address offset: 0xF14

Machine Hart ID

Contains the integer ID of the hardware thread running the code. Hart ID is unique for every VPR instance and this register's reset value is set to it


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x0000000E				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	HARTNUM										Machine Hart ID value

NORDIC.VPRNORDICCTRL

Address offset: 0x7C0

Nordic Core Control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	D	D	D	D	D	D	D	D									C	B						A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLERTPERIPH										Control bit to enable Real-Time Peripherals When this bit is cleared, it will override the APB read value of the INTEN register to 0.
			Disabled	0
			Enabled	1
B	RW	CNTIRQENABLE										Enables the generation of IRQ number COUNTER_IRQ_NUM
			Disabled	0x0
			Enabled	0x1
C	RW	VPRBUSPRI										Arbitration priority on bus Setting high priority will give VPR maximum priority and can cause starvation for other bus masters trying to access the same memory. It should only be used in limited sections of code and care must be taken to avoid continuous memory accesses to ensure other bus masters can perform interleaved accesses.
			LowPriority	0x0								Low priority for VPR RAM transactions on bus
			HighPriority	0x1								High priority for VPR RAM transactions on bus
D	W	NORDICKEY										Used in order to protect the write to this register
			Enabled	0x507D								Write enabled

NORDIC.VPRNORDICSLEEPCTRL

Address offset: 0x7C1

Nordic Sleep Control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																		C	B													A	A	A	A
Reset 0x00000002				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value								Description
A	RW	SLEEPSTATE										Sleep State
			WAIT	0x0								Sleep is not turning off the clock
			RESET	0x2								Sleep state default reset value. Going to sleep with sleep state = RESET has the same effect as going to sleep with sleep state = WAIT
			SLEEP	0x5								Sleep is turning the clock off
			DEEPSLEEP	0x7								Sleep is turning the clock off, equivalent to SLEEP This enumerator is deprecated.
			HIBERNATE	0xF								Sleep is turning the clock off and all the registers are saved automatically, restart by a reset
B	RW	RETURNTOSLEEP										Return to Sleep Forces the CPU to return to sleep when it returns in a non handler program
			Disabled	0x0
			Enabled	0x1
C	RW	STACKONSLEEP										Stack on Sleep Force CPU to stack the context before going to sleep : this is used in order to have a fast wake up
			Disabled	0x0
			Enabled	0x1

NORDIC.VPRNORDICFEATURESDISABLE

Address offset: 0x7C2

Contains disable bits for certain features in the core


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C	C	C	C	C	C	C	C	C	C	C	C	C	C	C	C												B	A
Reset 0x00000010				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DISABLECLICROUNDROBIN										Disable CLIC Round Robin Disable Round Robin arbitration in CLIC for interrupt requests
			Enabled	0
			Disabled	1
B	RW	UNRECOVRETURN										Unrecoverable Return Force unrecoverable return from exception
			Disabled	0
			Enabled	1
C	W	NORDICKEY										Used in order to protect the write to this register
			Enabled	0x507D								Write enabled

NORDIC.VIOPINS

Address offset: 0x7C3

VPR pins used for Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x000003FF				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	VAL										VPR pins used for Real Time Peripherals VIO

NORDIC.EXTPARAMS

Address offset: 0x7C4

Reads values of external configuration parameters

External configuration parameters are unique for every VPR instance and this register's reset value depends on them


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													C	C	C	C	B	A	A
Reset 0x0000000E				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	MULDIV										value of MULDIV
B	R	DBG										value of DBG
C	R	BKPT										value of BKPT

NORDIC.AXCACHE

Address offset: 0x7C5

Memory type encoding

AXI4 protocol memory type encoding


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																								C	C	C	C	B	B	B	B	A	A	A	A
Reset 0x00000EEE				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1	1	1	0	1	1	1	0
ID	R/W	Field	Value ID	Value								Description
A	RW	AWCACHE										Memory type for data stores
			DEVNONBUFF	0x0								Device Non-Bufferable
			DEVBUFF	0x1								Device Bufferable
			NNONCACHENONBUFF	0x2								Normal Non-cacheable Non-bufferable
			NNONCACHEBUFF	0x3								Normal Non-cacheable Bufferable
			WRITETHNALLOC	0x6								Write-through No-allocate
			WRITETHRALLOC	0x6								Write-through Read-allocate
			WRITETHWALLOC	0xE								Write-through Write-allocate
			WRITETHRWALLOC	0xE								Write-through Read and Write-allocate
			WRITEBACKNALLOC	0x7								Write-back No-allocate
			WRITEBACKRALLOC	0x7								Write-back Read-allocate
			WRITEBACKWALLOC	0xF								Write-back Write-allocate
			WRITEBACKRWALLOC	0xF								Write-back Read and Write-allocate
B	RW	IARCACHE										Memory type for instruction loads
			DEVNONBUFF	0x0								Device Non-Bufferable
			DEVBUFF	0x1								Device Bufferable
			NNONCACHENONBUFF	0x2								Normal Non-cacheable Non-bufferable
			NNONCACHEBUFF	0x3								Normal Non-cacheable Bufferable
			WRITETHNALLOC	0xA								Write-through No-allocate
			WRITETHRALLOC	0xE								Write-through Read-allocate
			WRITETHWALLOC	0xA								Write-through Write-allocate
			WRITETHRWALLOC	0xE								Write-through Read and Write-allocate
			WRITEBACKNALLOC	0xB								Write-back No-allocate
			WRITEBACKRALLOC	0xF								Write-back Read-allocate
			WRITEBACKWALLOC	0xB								Write-back Write-allocate
			WRITEBACKRWALLOC	0xF								Write-back Read and Write-allocate
C	RW	DARCACHE										Memory type for data loads
			DEVNONBUFF	0x0								Device Non-Bufferable
			DEVBUFF	0x1								Device Bufferable
			NNONCACHENONBUFF	0x2								Normal Non-cacheable Non-bufferable
			NNONCACHEBUFF	0x3								Normal Non-cacheable Bufferable
			WRITETHNALLOC	0xA								Write-through No-allocate
			WRITETHRALLOC	0xE								Write-through Read-allocate
			WRITETHWALLOC	0xA								Write-through Write-allocate
			WRITETHRWALLOC	0xE								Write-through Read and Write-allocate
			WRITEBACKNALLOC	0xB								Write-back No-allocate
			WRITEBACKRALLOC	0xF								Write-back Read-allocate
			WRITEBACKWALLOC	0xB								Write-back Write-allocate
			WRITEBACKRWALLOC	0xF								Write-back Read and Write-allocate

NORDIC.CACHE.CTRL

Address offset: 0x7C8

Cache control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			B																A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable cache
			Disabled	0								Cache disabled
			Enabled	1								Cache enabled
B	RW W1S	CACHECLR										Cache clear Writing this bit writes the tag cache region to 0. This should be done before enabling the cache. The CPU stalls until the operation is complete. Interrupts must be disabled when performing the cache clear operation.
			NoOperation	0								No Operation
			Clear	1								Cache clear

NORDIC.CACHE.CFG

Address offset: 0x7C9

Cache configuration

Configures the cache region size and line size


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																											B					A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CACHESIZE		0..15								Cache size is 2^CACHESIZE or (1 << CACHESIZE) KB, with a maximum size of 32KB (CACHESIZE = 5) To prevent RAM corruption or undefined behavior this field should only be modified when the cache is disabled
B	RW	CACHELINESIZE										Cache line size To prevent RAM corruption or undefined behavior this field should only be modified when the cache is disabled
			CachelineSize32B	0								Cache line size is 32 bytes (4 data units)
			CachelineSize64B	1								Cache line size is 64 bytes (8 data units)

NORDIC.CACHE.DATATAGADDR

Address offset: 0x7CA

Cache tag base address


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL		0x0..0xFFFFFFFC								Cache tag base address value Defines where the tag cache region starts. The tag base address must be aligned with the tag cache region size. The lower 2 bits are write ignored / read as zero, so the value must be rounded to a power of 2.

NORDIC.CACHE.DATABASEADDR

Address offset: 0x7CB

Cache data base address


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL		0x0..0xFFFFFFFC								Cache data base address value Defines where the data cache region starts. The data base address must be aligned with the data cache region size. The lower 2 bits are write ignored / read as zero, so the value must be rounded to a power of 2.

NORDIC.RTPERIPHCTRL

Address offset: 0x7CC

RT peripheral control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID															F			E	E	D	D	D	D				C				B				A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CLOCKPOLARITY										Clock polarity This field is applicable only when OUTMODE.MODE = OutBBufToggleClk
			Low	0x0								Clock polarity is low
			High	0x1								Clock polarity is High
B	RW	STOPCOUNTERS										Stop counters CNT0 and CNT1 on OUTB under-run, or on INB Overflow if OUTMODE2 and INMODE2 This feature is used for clock stretching during OUTB under-run
			NoStop	0								Counters do not stop on OUTB under-run
			Stop	1								Counters stop on OUTB under-run Resume the counters when OUTB is written
C	RW	INSEL										Input pin selection
			SamePin	0x0								Sample on same OUT pin
			SeparatePin	0x1								Sample on separate pin (OUT+1)
D	RW	EVPINSEL										Event pin select Event pin select: VIO 0-15
E	RW	EVEDGE										Event pin edge
			AnyEdge	0x0								Any edge
			RisingEdge	0x1								Rising edge
			FallingEdge	0x2								Falling edge
F	RW	EVSAMPLE										Event pin sampling
			Continuous	0x0								Sample continuously
			Event	0x1								Sample on CNT1 event

NORDIC.RTPERIPHSTATUS

Address offset: 0x7CD

Real-Time Peripheral Status

Reads Real-Time Peripheral Status. Write to clear status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	OUTBUNDERRUN										Set if OUTB value is not written in time for the next shift out event, which means OUT data is not valid. Can only be cleared by SW by writing a 1 to the bit.
B	RW W1C	INBOVERRUN										Set if INB value is not read in time for the next shift in event, which means IN data is lost. Can only be cleared by SW by writing a 1 to the bit.

NORDIC.CNTMODE0

Address offset: 0x7D0

CNT0 Mode

Real Time Peripherals VTIM


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CNTMODE0										CNT0 Mode
			STOP	0x0								CNT0 stops at 0
			WRAP	0x1								When CNT0 reaches 0 it will continue counting from 0xFFFF
			RELOAD	0x2								When CNT0 reaches 0 it will continue counting from the value in CNTTOP
			TRIGCOMB	0x3								When CNT0 reaches 0 it is reloaded from CNTTOP and stops. Counting will restart when a VIO event happens
			TRIGWRAP	0x5								When the counter reaches 0 it wraps to MAX and stops. Counting will restart when a VIO event happens

NORDIC.CNTMODE1

Address offset: 0x7D1

CNT1 Mode

Real Time Peripherals VTIM


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CNTMODE1										CNT1 Mode
			STOP	0x0								CNT1 stops at 0
			WRAP	0x1								When CNT1 reaches 0 it will continue counting from 0xFFFF
			RELOAD	0x2								When CNT1 reches 0 it will continue counting from the value in CNTTOP
			TRIGCOMB	0x3								In combine mode mode CNT1 acts as an extension of CNT0 (16 most significant bits of the 32-bit CNT)
			TRIGRELOAD	0x4								When CNT1 reaches 0 it is reloaded from CNTTOP and stops. Counting will restart when a VIO event happens
			TRIGWRAP	0x5								When CNT1 reaches 0 it wraps to MAX and stops. Counting will restart when a VIO event happens

NORDIC.CNT

Address offset: 0x7D2

32-bit Counter

Addresses CNT0 and CNT1 in the same operation. Real Time Peripherals VTIM


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CNT0										16-bit Counter 0
B	RW	CNT1										16-bit Counter 1

NORDIC.CNTTOP

Address offset: 0x7D3

Counter Top

This register value is used when reload mode is active. Entire 32-bit value is used when CNT1 is in combined mode. Real Time Peripherals VTIM


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CNT0RELOAD										Reload value for CNT0
B	RW	CNT1RELOAD										Reload value for CNT1

NORDIC.CNTADD

Address offset: 0x7D4

CNT Add

Adds a value to 32-bit counter CNT. Real Time Peripherals VTIM


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	VAL										Value added to CNT

NORDIC.CNT0

Address offset: 0x7D5

16-bit Counter 0

Real Time Peripherals VTIM

Read-only when the counters are in COMBINE mode.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										CNT0 value

NORDIC.CNTADD0

Address offset: 0x7D6

CNT0 Add

Adds a value to CNT0. Real Time Peripherals VTIM

Has no effect when the counters are in COMBINE mode.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	VAL										Value added to CNT0

NORDIC.CNT1

Address offset: 0x7D7

16-bit Counter 1

Real Time Peripherals VTIM

Read-only when the counters are in COMBINE mode.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										CNT1 value

NORDIC.CNTADD1

Address offset: 0x7D8

CNT1 Add

Adds a value to CNT1. Real Time Peripherals VTIM

Has no effect when the counters are in COMBINE mode.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	VAL										Value added to CNT1

NORDIC.WAIT0

Address offset: 0x7DA

Wait 0

Writing to this register will stall the CPU until CNT0 reaches 0

Note: This should not be used when counters are in combined mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DATA										Value to write to CNT0
B	W	WRITEDATA
			WAIT	0x0								Wait until CNT0 reaches 0
			WRITE	0x1								Write DATA to CNT0 and then wait until CNT0 reaches 0

NORDIC.WAIT1

Address offset: 0x7DB

Wait 1

Writing to this register will stall the CPU until CNT1 reaches 0

Note: This should not be used when counters are in combined mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DATA										Value to write to CNT1
B	W	WRITEDATA
			WAIT	0x0								Wait until CNT1 reaches 0
			WRITE	0x1								Write DATA to CNT1 and then wait until CNT1 reaches 0

NORDIC.WAIT

Address offset: 0x7DC

Wait

Writing any value to register will stall the CPU until CNT reaches 0 in TRIGCOMB mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	VAL

NORDIC.TASKS

Address offset: 0x7E0

DPPI Tasks

CSR view of TASKS_TRIGGER[31:0] APB registers. Real Time Peripherals VEVIF


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	RW	TASKS[i] (i=0..31)
			Disabled	0x0								TASKS[i] diabled
			Enabled	0x1								TASKS[i] enabled

Address offset: 0x7E1

Enable Task Subscription

CSR view of SUBSCRIBE_TRIGGER[31:0] APB registers (Enable bits). Real Time Peripherals VEVIF


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
	RW	SUBSCRIBE[i] (i=16..19)
			Disabled	0x0								Subscribe disabled for TASK[i]
			Enabled	0x1								Subscribe enabled for TASK[i]

NORDIC.EVENTS

Address offset: 0x7E2

DPPI Events

CSR view of EVENTS_TRIGGERED[31:0]APB registers. Real Time Peripherals VEVIF


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	RW	EVENTS[i] (i=0..31)
			Disabled	0x0								EVENTS[i] disabled
			Enabled	0x1								EVENTS[i] enabled

NORDIC.PUBLISH

Address offset: 0x7E3

Enable Event Publication

CSR view of PUBLISH_TRIGGERED[31:0] APB registers (Enable bits). Real Time Peripherals VEVIF


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
	RW	PUBLISH[i] (i=16..19)
			Disabled	0x0								Publish disabled for EVENTS[i]
			Enabled	0x1								Publish enabled for EVENTS[i]

NORDIC.INTEN

Address offset: 0x7E4

DPPI Event Interrupt Enable

CSR view of the INTEN APB register (also modified through INTENSET and INTENCLR). Every bit enables interrupt generation sourced by the corresponding event. Real Time Peripherals VEVIF


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	RW	INTEN[i] (i=0..31)
			Disabled	0x0								Interrupt disabled for EVENTS[i]
			Enabled	0x1								Interrupt enabled for EVENTS[i]

NORDIC.EVENTSB

Address offset: 0x7E5

Buffered DPPI Events

The value in this register is passed to EVENTS on a Counter0 event (write sets dirty status). Real Time Peripherals VEVIF


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	W	EVENTSB[i] (i=0..31)
			Disabled	0x0								EVENTSB[i] disabled
			Enabled	0x1								EVENTSB[i] enabled

NORDIC.EVENTSBS

Address offset: 0x7E6

EVENTSB Dirty Status

Reads EVENTSB dirty status. Writes EVENTSB (sets dirty status)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	EVENTSB										Write to EVENTSB (if not dirty)
A	R	DIRTYBIT										Read EVENTSB Dirty status
			CLEAN	0x0								Buffer is clean
			DIRTY	0x1								Buffer is dirty

NORDIC.OUT

Address offset: 0xBC0

GPIO Output value. Real Time Peripherals VIO.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	RW	PIN[i] (i=0..15)
			LOW	0x0								Pin driver is low
			HIGH	0x1								Pin driver is high

NORDIC.DIR

Address offset: 0xBC1

GPIO pin Direction. Real Time Peripherals VIO.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	RW	PIN[i] (i=0..15)
			INPUT	0x0								Pin is set as input
			OUTPUT	0x1								Pin is set as output

NORDIC.IN

Address offset: 0xBC2

GPIO Input. Real Time Peripherals VIO.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	R	PIN[i] (i=0..15)
			LOW	0x0								Pin is Low
			HIGH	0x1								Pin is High

NORDIC.INMODE

Address offset: 0xBC3

Input Mode

Sets the sampling mode for values read through IN. Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MODE										Input Mode
			CONTINUOUS	0x0								Continuous sampling (if CPU is not sleeping)
			EVENT	0x1								Sampling on Counter1 event
			SHIFT	0x2								Sampling and shifting on Counter1 event synchronized with OUT
			SHIFTA	0x3								Sampling and shifting on Counter1 event, independent of OUT

NORDIC.OUTB

Address offset: 0xBC4

Buffered GPIO Output

Bits 15:0 in this register are passed to OUT on a Counter0 event (write sets dirty status). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	RW	PIN[i] (i=0..31)
			LOW	0x0								Pin driver is low
			HIGH	0x1								Pin driver is high

NORDIC.DIRB

Address offset: 0xBC5

Buffered GPIO pin Direction

The value in this register is passed to DIR on a Counter0 event (write sets dirty status). Real Time Peripherals VIO.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	RW	PIN[i] (i=0..15)
			INPUT	0x0								Pin is set as input
			OUTPUT	0x1								Pin is set as output

NORDIC.DIROUT

Address offset: 0xBC6

DIR and OUT concatenation

Addresses DIR[15:0] and OUT[15:0] in the same operation. Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	OUT										GPIO Output
B-Q	RW	DIR[i] (i=0..15)										GPIO pin Direction

NORDIC.DIROUTB

Address offset: 0xBC7

Concatenation of DIRB and OUTB

Addresses DIRB[15:0] and OUTB[15:0] in the same operation. The value in this register is passed to DIROUT on a Counter0 event (write sets dirty status of both buffers). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	OUTB										Buffered GPIO Output
B-Q	RW	DIRB[i] (i=0..15)										Buffered GPIO pin Direction

NORDIC.OUTBRB

Address offset: 0xBC8

Byte reversed register OUTB

This register is shadow to register OUTB and holds frames in reversed order for each byte of OUTB


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL		0x0..0xFFFFFFFF

NORDIC.OUTBRW

Address offset: 0xBC9

Word reversed register OUTB

This register is shadow to register OUTB and holds frame reversed in the whole word of OUTB


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL		0x0..0xFFFFFFFF

NORDIC.INBRB

Address offset: 0xBCA

Byte reversed register INB

This register is shadow to register INB and holds frame reversed in each byte of OUTB


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VAL		0x0..0xFFFFFFFF

NORDIC.SHIFTCTRLB

Address offset: 0xBCB

Buffered IO shift control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID								B_C	B_C	B_C	B_C			C_A	C_A				B_B	B_B	B_B	B_B	B_B		B_A	B_A	B_A			A_A	A_A	A_A	A_A	A_A	A_A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	SHIFTCNTB
A_A	RW	SHIFTCNTB.VALUE		0..63								Alias to SHIFTCNTB.VALUE register
B	RW	OUTMODEB
B_A	RW	OUTMODEB.MODE										Alias to OUTMODEB.MODE register
			NoShifting	0x0								No shifting
			OutBBuf	0x2								Only OUTB used for buffering
			OutBBufToggleClk	0x4								Only OUTB used for buffering, auto-toggle clock line
B_B	RW	OUTMODEB.FRAMEWIDTH		0..16								Alias to OUTMODEB.FRAMEWIDTH register
B_C	RW	OUTMODEB.SEL		0..15								Alias to OUTMODEB.SEL register
C	RW	INMODEB
C_A	RW	INMODEB.MODE										Alias to INMODEB.MODE register
			CONTINUOUS	0x0								Continuous sampling (if CPU is not sleeping)
			EVENT	0x1								Sampling on Counter1 event
			SHIFT	0x2								Sampling and shifting on Counter1 event
			SHIFTA	0x3								Sampling and shifting on Counter1 event, independent from output

NORDIC.SHIFTCNTIN

Address offset: 0xBCD

Number of frames to be shifted from INB before new data is required


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE		0..63								Value

NORDIC.SHIFTCNTOUT

Address offset: 0xBCE

Number of frames to be shifted to OUTB before new data is required


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE		0..63								Value

NORDIC.SHIFTCNTB

Address offset: 0xBCF

Buffered SHIFTCNTOUT and SHIFTCNTIN register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE		0..63								Value

NORDIC.OUTTGL

Address offset: 0xBD0

GPIO Output Toggle

Toggles bits in OUT. Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	W	PIN[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled

NORDIC.DIRTGL

Address offset: 0xBD1

GPIO pin Direction Toggle

Toggles bits in DIR. Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	W	PIN[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled

NORDIC.OUTBTGL

Address offset: 0xBD2

Buffered GPIO Output Toggle

Toggles bits in OUTB (sets dirty status). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	W	PIN[i] (i=0..31)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled

NORDIC.DIRBTGL

Address offset: 0xBD3

Buffered GPIO pin Direction Toggle

Toggles bits in DIRB (sets dirty status). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	W	PIN[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled

NORDIC.DIROUTTGL

Address offset: 0xBD4

DIROUT Toggle

Toggles bits in DIR[15:0] and OUT[15:0] in the same operation. Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	W	OUT[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled
Q-f	W	DIR[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled

NORDIC.DIROUTBTGL

Address offset: 0xBD5

DIROUTB Toggle

Toggles bits in DIRB[15:0] and OUTB[15:0] in the same operation (sets dirty status). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	W	OUTB[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled
Q-f	W	DIRB[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled

NORDIC.OUTUBTGL

Address offset: 0xBD6

Buffered GPIO Unshifted Output Toggle

Toggles bits in OUTUB[15:0] (sets dirty status). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-P	W	PIN[i] (i=0..15)
			UNCHANGED	0x0								Pin remains unchanged
			TOGGLE	0x1								Pin is toggled

NORDIC.OUTBS

Address offset: 0xBD8

Buffered GPIO Output Dirty Status

Reads OUTB dirty status. Writes OUTB value (and sets dirty status) if it's not already dirty. Real Time Peripherals VIO

Note: This register does not stall on writes when already dirty, and as such can be used to implement non-blocking update-when-ready writes to the buffered outputs


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	OUTB										Write to OUTB (if not dirty)
A	R	DIRTYBIT										Read Buffer Dirty status
			CLEAN	0x0								Buffer is clean
			DIRTY	0x1								Buffer is dirty

NORDIC.DIRBS

Address offset: 0xBD9

Buffered GPIO pin Direction Dirty Status

Reads DIRB dirty status. Writes DIRB value (sets dirty status). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIRB										Write to DIRB (if not dirty)
A	R	DIRTYBIT										Read Buffer Dirty status
			CLEAN	0x0								Buffer is clean
			DIRTY	0x1								Buffer is dirty

NORDIC.DIROUTBS

Address offset: 0xBDA

Combination of DIRB and OUTB Dirty Status

Reads combination (OR) of DIRB and OUTB dirty status. Writes DIRB and OUTB[15:0] in the same operation (sets dirty status of both buffers). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	DIROUTB										Write to DIROUTB (if not dirty)
A	R	DIRTYBIT										Read Combination (OR) of DIRB and OUTB Dirty status
			CLEAN	0x0								Buffer is clean
			DIRTY	0x1								Buffer is dirty

NORDIC.OUTUBS

Address offset: 0xBDB

Buffered GPIO Unshifted Output Dirty Status

Reads OUTUB dirty status. Writes OUTUB[15:0] value (sets dirty status). Real Time Peripherals VIO


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	OUTUB										Write to OUTUB (if not dirty)
A	R	DIRTYBIT										Read Buffer Dirty status
			CLEAN	0x0								Buffer is clean
			DIRTY	0x1								Buffer is dirty

NORDIC.OUTMODE

Address offset: 0xBE3

Serial output mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID								C	C	C	C				B	B	B	B	B														A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MODE										Mode
			NoShifting	0x0								No shifting
			OutBBuf	0x2								Only OUTB used for buffering
			OutBBufToggleClk	0x4								Only OUTB used for buffering, auto-toggle clock line
B	RW	FRAMEWIDTH		0..16								Output frame width MODE=0x2: BITS=FRAMEWIDTH. Legal values: 1, 2, 3, 4, 5, 6, 7, 8, 16 (9-15 are not legal) MODE=0x4: BITS=FRAMEWIDTH. Legal values: 1, 2, 3, 4, 5, 6, 7, 8
C	RW	SEL		0..15								Start index of VIO used for shifting from OUTB and to INB. For OUTB, the number of left shifts is given by (MODE is OUTMODE.MODE): if (MODE < 2) then SHIFTS = 0; else if ((MODE==4) & (SEL==0)) then SHIFTS = 1; else SHIFTS = SEL; For INB, the number of left shifts is given by (MODE is INMODE.MODE): if (MODE < 2) then SHIFTS = 0; else if ((MODE==2) & (INSEL==1) & (FRAMEWIDTH==1)) then SHIFTS = 2; else if (SEL==0) then SHIFTS = 1; else SHIFTS = SEL;

NORDIC.OUTMODEB

Address offset: 0xBE4

Buffered OUTMODE register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID								C	C	C	C				B	B	B	B	B														A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MODE										Mode
			NoShifting	0x0								No shifting
			OutBBuf	0x2								Only OUTB used for buffering
			OutBBufToggleClk	0x4								Only OUTB used for buffering, auto-toggle clock line
B	RW	FRAMEWIDTH		0..16								Frame width in bits
C	RW	SEL		0..15								Start index of VIO used for shifting from OUTB and to INB. For OUTB, the number of left shifts is given by (MODE is OUTMODE.MODE): if (MODE < 2) then SHIFTS = 0; else if ((MODE==4) & (SEL==0)) then SHIFTS = 1; else SHIFTS = SEL; For INB, the number of left shifts is given by (MODE is INMODE.MODE): if (MODE < 2) then SHIFTS = 0; else if ((MODE==2) & (INSEL==1) & (FRAMEWIDTH==1)) then SHIFTS = 2; else if (SEL==0) then SHIFTS = 1; else SHIFTS = SEL;

NORDIC.INMODEB

Address offset: 0xBE5

Buffered INMODE register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MODE										Input Mode
			CONTINUOUS	0x0								Continuous sampling (if CPU is not sleeping)
			EVENT	0x1								Sampling on Counter1 event
			SHIFT	0x2								Sampling and shifting on Counter1 event
			SHIFTA	0x3								Sampling and shifting on Counter1 event, independent from output

NORDIC.INB

Address offset: 0xBE6

Buffered GPIO input

GPIO Input. Real Time Peripherals VIO.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	R	PIN[i] (i=0..31)
			LOW	0x0								Pin is Low
			HIGH	0x1								Pin is High

NORDIC.OUTUB

Address offset: 0xBE7

Buffered write to Unshifted parts of OUT

Buffered write to OUT bits that are not driven by OUTB shifting (OUT[OUTMODE.FRAMEWIDTH+SHIFTS-1:SHIFTS] is not affected, refer to OUTMODE.SEL for the definition of SHIFTS). OUTUB is transferred to OUT on a selectable internal event.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	OUT										Written to OUT MSBs that are not driven by OUTB shifting.

NORDIC.SHIFTCNTCOMP

Address offset: 0xBE8

SHIFTCNTIN/OUT compare values

Can trigger events and interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																						B	B	B	B	B	B			A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	OUTCOMPVAL										Compare value for SHIFTCNTOUT
B	RW	INCOMPVAL										Compare value for SHIFTCNTIN

NORDIC.WAITEVENT

Address offset: 0xBE9

Wait for internal event

Write value: mask which bits to wait for

Read value: the new value when unstalled. If a read-while-write operation is performed, the read value is AND’ed with the write value


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	IEVENTCNT0										CNT0's event
B	RW	IEVENTCNT1										CNT1's event
C	RW	IEVENTVIO										Event generated by a specific VIO pin
D	RW	IEVENTVIOANY										Event generated by a change in any VIO pin
E	RW	IEVENTVTASKSANY										Event when any TASK is triggered
F	RW	IEVENTSHIFTCNTOUT										Event for SHIFTCNTOUT when reaching a compare value defined in SHIFTCNTCOMP
G	RW	IEVENTSHIFTCNTIN										Event for SHIFTCNTIN when reaching a compare value defined in SHIFTCNTCOMP

NORDIC.WAITINPUT

Address offset: 0xBEA

Wait input

Each bit waits until either the corresponding VTASK is high or there is a change in the corresponding VIO pin. Whether a given bit is mapped to VEVIF or VIO is defined by CSR VIOPINS, which can be different for each VPR instance.

Write value: mask which bits to wait for

Read value: bits that contribute to unstalling will read as 1, other bits will read as 0. If a read-while-write operation is performed, the read value is AND’ed with the write value


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VTASKSVIO										VTASKS or VIO pins

NORDIC.RTPINTEN

Address offset: 0xBEB

Interrupt enable


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CNT0										Interrupt enable for IEVENTCNT0, alias of VPRNORDICCTRL.CNTIRQENABLE
B	RW	CNT1										Interrupt enable for IEVENTCNT1
C	RW	VIO										Interrupt enable for IEVENTVIO
D	RW	VIOANY										Interrupt enable for IEVENTVIOANY
E	RW	VTASKSANY										Interrupt enable for IEVENTVTASKSANY
F	RW	SHIFTCNTOUT										Interrupt enable for IEVENTSHIFTCNTOUT
G	RW	SHIFTCNTIN										Interrupt enable for IEVENTSHIFTCNTIN

NORDIC.OUTUBTRIG

Address offset: 0xBEC

OUTUB trigger select

Selects an internal event as the trigger condition for transferring OUTUB to OUT


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	SEL										OUTUBTRIG select
			IEVENTSHIFTCNTIN	6
			IEVENTSHIFTCNTOUT	5
			IEVENTVTASKSANY	4
			IEVENTVIOANY	3
			IEVENTVIO	2
			IEVENTCNT1	1
			IEVENTCNT0	0

VPR — RISC-V CPU

VPR registers

Instances

Configuration

Register overview

TASKS_TRIGGER[n]

SUBSCRIBE_TRIGGER[n]

EVENTS_TRIGGERED[n]

PUBLISH_TRIGGERED[n]

INTEN

INTENSET

INTENCLR

INTPEND

DEBUGIF.DATA0

DEBUGIF.DATA1

DEBUGIF.DMCONTROL

DEBUGIF.DMSTATUS

DEBUGIF.HARTINFO

DEBUGIF.HALTSUM1

DEBUGIF.HAWINDOWSEL

DEBUGIF.HAWINDOW

DEBUGIF.ABSTRACTCS

DEBUGIF.ABSTRACTCMD

DEBUGIF.ABSTRACTAUTO

DEBUGIF.CONFSTRPTR[n]

DEBUGIF.NEXTDM

DEBUGIF.PROGBUF[n]

DEBUGIF.AUTHDATA

DEBUGIF.HALTSUM2

DEBUGIF.HALTSUM3

DEBUGIF.SBADDRESS3

DEBUGIF.SBCS

DEBUGIF.SBADDRESS0

DEBUGIF.SBADDRESS1

DEBUGIF.SBADDRESS2

DEBUGIF.SBDATA0

DEBUGIF.SBDATA1

DEBUGIF.SBDATA2

DEBUGIF.SBDATA3

DEBUGIF.HALTSUM0

CPURUN

VPRSTATUS

INITPC

VPR CLIC registers

Instances

Configuration

Register overview

CLIC.CLICCFG

CLIC.CLICINFO

CLIC.CLICINT[n]

VPR Control Status Registers (CSRs)

Instances

Configuration

Register overview

MSTATUS

MISA

MTVEC

MTVT

MCOUNTINHIBIT

MSCRATCH

MEPC

MCAUSE

MTVAL

MINTSTATUS

MINTTHRESH

MCLICBASE

TSELECT

TDATA1

TDATA2

TDATA3

TINFO

TCONTROL

DCSR

DPC

MCYCLE

MINSTRET

MCYCLEH

MINSTRETH

UCYCLE

UINSTRET