SPIM Electrical specification

Timing specifications


Symbol	Description	Min.	Typ.	Max.	Units
f_SPIM	Bit rates for SPIM¹			8	Mbps
t_SPIM,START	Time from START task to transmission started		1		µs
t_SPIM,CSCK	SCK period	31.25			ns
t_SPIM,WHSCK	SCK high time^a	(t_CSCK/2) - t_RSCK - 1.5 ns
t_SPIM,WLSCK	SCK low time^a	(t_CSCK/2) - t_FSCK - 1.5 ns

SPI master timing diagram — Figure 1. SPIM timing diagram

¹ High bit rates may require GPIOs to be set as High Drive or Extra High Drive, see GPIO chapter for more details.

Timing specifications for GPIO port P0 using Standard drive strength


Symbol	Description	Min.	Typ.	Max.	Units
t_SPIM,SUMI	SDI to CLK edge setup time	47			ns
t_SPIM,HMI	CLK edge to SDI hold time	0			ns
t_SPIM,VMO	CLK edge to SDO valid			11	ns
t_SPIM,HMO	SDO hold time after CLK edge	-4			ns

Timing specifications for GPIO port P0 using High drive strength


Symbol	Description	Min.	Typ.	Max.	Units
t_SPIM,SUMI	SDI to CLK edge setup time	44			ns
t_SPIM,HMI	CLK edge to SDI hold time	0			ns
t_SPIM,VMO	CLK edge to SDO valid			15	ns
t_SPIM,HMO	SDO hold time after CLK edge	-4			ns

Timing specifications for GPIO port P1 using Standard drive strength


Symbol	Description	Min.	Typ.	Max.	Units
t_SPIM,SUMI	SDI to CLK edge setup time	34			ns
t_SPIM,HMI	CLK edge to SDI hold time	0			ns
t_SPIM,VMO	CLK edge to SDO valid			5	ns
t_SPIM,HMO	SDO hold time after CLK edge	-4			ns

Timing specifications for GPIO port P1 using High drive strength


Symbol	Description	Min.	Typ.	Max.	Units
t_SPIM,SUMI	SDI to CLK edge setup time	31			ns
t_SPIM,HMI	CLK edge to SDI hold time	0			ns
t_SPIM,VMO	CLK edge to SDO valid			7	ns
t_SPIM,HMO	SDO hold time after CLK edge	-6			ns