☰
PDF Docs

Revision history
About this document
Document status
Peripheral chapters
Register overview table
Register tables
Registers
Product overview
Block diagram
Product overview
Power domains
Address format
Memory
CPU
CPUC — CPU control
Instantiation
AMBA interconnect (AMBIX)
EasyDMA
CACHE — Instruction/data cache
FICR — Factory information configuration registers
MEMCONF — Memory configuration
RRAMC — Resistive random access memory controller
SICR — Secure information configuration region
SWI — Software interrupts
UICR — User information configuration registers
Power and clock management
System ON mode
System OFF mode
System Hibernation mode
Power supply supervisors
CLOCK — Clock control
OSCILLATORS — Oscillator control
POWER — Power control
REGULATORS — Regulator control
RESET — Reset control
Event system
DPPI latencies
DPPI — Distributed programmable peripheral interconnect
PPIB — PPI Bridge
Security
Memory and peripheral access permissions
TrustZone security
Immutable boot region
Security attributes
Security fault
Peripherals with split security access
Physical security
CRACEN — Cryptographic accelerator engine
GLITCHDET — Voltage glitch detectors
KMU — Key management unit
MPC — Memory Privilege Controller
SPU — System protection unit
TAMPC — Tamper controller
Peripherals
Peripheral interface
Instantiation
AAR — Accelerated address resolver
CCM — AES CCM mode encryption
COMP — Comparator
ECB — AES electronic codebook mode encryption
EGU — Event generator unit
GPIO — General purpose input/output
GPIOTE — GPIO tasks and events
GRTC — Global real-time counter
LPCOMP — Low-power comparator
RADIO — 2.4 GHz radio
SAADC — Successive approximation analog-to-digital converter
SPIM — Serial peripheral interface controller with EasyDMA
SPIS — Serial peripheral interface target with EasyDMA
TEMP — Temperature sensor
TIMER — Timer/counter
TWIM — I2C compatible two-wire interface controller with EasyDMA
TWIS — I2C compatible two-wire interface target with EasyDMA
UARTE — Universal asynchronous receiver/transmitter with EasyDMA
VPR — RISC-V CPU
WDT — Watchdog timer
Debug and trace
Debug access port
Access port protection
Debug Interface mode
Real-time debug
Multidrop serial wire debug
Trace
CTRL-AP — Control access port
TAD — Trace and debug control
ETM — Embedded trace macrocell
TPIU — Trace port interface unit
Pin assignments
QFN48 6x6 mm package
CSP29 (CAAA) package
CSP39 (CBAA) package
Reference circuitry
Reflow conditions
Electrical specifications
Conditions
Current consumption
CLOCK Electrical specification
CPU Electrical specification
GPIO Electrical specification
OSCILLATORS Electrical specification
PPI Electrical specification
REGULATORS Electrical specification
RRAMC Electrical specification
SPIM Electrical specification
SPIS Electrical specification
SWDP Electrical specification
TWIM Electrical specification
TWIS Electrical specification
UARTE Electrical specification
WDT Electrical specification
- Watchdog Timer Electrical Specification
Recommended operating conditions
CSP light sensitivity
Absolute maximum ratings
Device marking
Order code
Code ranges and values
Product options
Preprogrammed firmware
Legal notices

WDT Electrical specification

Watchdog Timer Electrical Specification


Symbol	Description	Min.	Typ.	Max.	Units
t_WDT	Time out interval	458 µs		36 h

← Previous UARTE Electrical specification Next → Recommended operating conditions

Generated from PDF using pdfmine.