SWI — Software interrupts
A set of interrupts have been reserved for use as software interrupts.
These interrupts can be enabled and triggered by software by using the Arm® Cortex®-M33 NVIC registers, as described in the Arm Cortex-M33 Processor Technical Reference Manual.
Registers
Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
| SWI00 | APPLICATION | 0x5001C000 | HF | S | NA | No | Software interrupt SWI00 |
| SWI01 | APPLICATION | 0x5001D000 | HF | S | NA | No | Software interrupt SWI01 |
| SWI02 | APPLICATION | 0x5001E000 | HF | S | NA | No | Software interrupt SWI02 |
| SWI03 | APPLICATION | 0x5001F000 | HF | S | NA | No | Software interrupt SWI03 |