USBREG — USB regulator control

A 5 V USB supply must power the VBUS pin when using the USB peripheral.

The device has a dedicated internal voltage regulator for converting the VBUS supply to 3.3 V for the USB signaling interface (D+ and D- lines, and pull-up on D+). The rest of the USB peripheral (USBHS) is supplied through the main supply like other on-chip features. As a consequence, both VBUS and VDD are required for USB peripheral operation. For details on the device voltage regulators, see REGULATORS — Regulator control.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
VREGUSB : S VREGUSB : NS	GLOBAL	0x50121000 0x40121000	US	S	NA	No	USB regulator

Configuration


Instance	Domain	Configuration
VREGUSB : S VREGUSB : NS	GLOBAL

Register overview


Register	Offset	Description
TASKS_START	0x000	Enable and start VREGUSB so that it can detect VBUS
TASKS_STOP	0x004	Stop and disable VREGUSB
EVENTS_VBUSDETECTED	0x104	VBUS detected
EVENTS_VBUSREMOVED	0x110	VBUS removed
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
INTPEND	0x30C	Pending interrupts

TASKS_START

Address offset: 0x000

Enable and start VREGUSB so that it can detect VBUS


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_START										Enable and start VREGUSB so that it can detect VBUS
			Trigger	1								Trigger task

TASKS_STOP

Address offset: 0x004

Stop and disable VREGUSB


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_STOP										Stop and disable VREGUSB
			Trigger	1								Trigger task

EVENTS_VBUSDETECTED

Address offset: 0x104

VBUS detected


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_VBUSDETECTED										VBUS detected
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_VBUSREMOVED

Address offset: 0x110

VBUS removed


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_VBUSREMOVED										VBUS removed
			NotGenerated	0								Event not generated
			Generated	1								Event generated

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															B			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VBUSDETECTED										Enable or disable interrupt for event VBUSDETECTED
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	VBUSREMOVED										Enable or disable interrupt for event VBUSREMOVED
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															B			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	VBUSDETECTED										Write '1' to enable interrupt for event VBUSDETECTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	VBUSREMOVED										Write '1' to enable interrupt for event VBUSREMOVED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															B			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1C	VBUSDETECTED										Write '1' to disable interrupt for event VBUSDETECTED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1C	VBUSREMOVED										Write '1' to disable interrupt for event VBUSREMOVED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTPEND

Address offset: 0x30C

Pending interrupts


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															B			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	VBUSDETECTED										Read pending status of interrupt for event VBUSDETECTED
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
B	R	VBUSREMOVED										Read pending status of interrupt for event VBUSREMOVED
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending