GPIO — General purpose input/output

The GPIO port peripheral implements up to 32 pins, PIN[n] (n = 0..31), that can be individually configured in the PIN_CNF[n] registers (n=0..31).

The following parameters can be enabled or configured in these registers:

• Direction
• Drive strength
• Pull-up and pull-down resistors
• Pin sensing
• Input buffer disconnect
• Analog input (for selected pins)

All write-capable registers are retained registers. See POWER — Power control for more information.

When not used as an input, disconnect the input buffer of the GPIO pin to save power. An input must be connected to get a valid value in the IN register and for the sense mechanism to have access to the pin.

Other peripherals in the system can connect to GPIO pins to override their output value, override their configuration, or read their analog or digital input value.

Selected pins also support analog input signals (ANAIN). The assignment of the analog pins can be found in Pin assignments.

GPIO drive strength is configured using the DRIVE0 and DRIVE1 fields of register PIN_CNF[n] (n=0..31) (Retained). Some pins may not support every drive configuration, see Pin assignments for more information.

When a pin is configured as digital input, it is important to minimize increased current consumption when the input voltage is between V_IL and V_IH. It is a good practice to ensure that the external circuitry does not drive the pin to levels between V_IL and V_IH for a long period of time.

For more information on pin assignment and the corresponding effect of read and write operations of GPIO registers, see Peripheral and subsystem assignment.

Pin sensitivity can be individually configured through the SENSE field in the PIN_CNF[n] register to detect a high level or a low level on their input. When the correct level is detected, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal.

The default behavior for the DETECT signal is defined by the register DETECTMODE. By default, the DETECT signals from all pins in the GPIO port are combined into one common DETECT signal that is routed throughout the system, and can be utilized by other peripherals. This mechanism is functional in both System ON and System OFF modes.The DETECTMODE applies to both secure and non-secure pins.

Pins must be in a level that cannot trigger the sense mechanism before enabling it. When the sense mechanism is enabled, the DETECT signal will immediately go high if the SENSE condition configured in the PIN_CNF registers is met. This will trigger a PORT event if the DETECT signal was low before enabling the sense mechanism.

The DETECT signal is used by the power and clock management system to exit from System OFF mode, and by the GPIOTE peripheral to allow pins to generate events and interrupts.

When a pin's PINx.DETECT signal goes high, a flag will be set in the register LATCH. For example, when the PIN0.DETECT signal goes high, bit 0 in the register LATCH will be set to 1. If the CPU performs a clear operation on a bit in the register LATCH when the associated PINx.DETECT signal is high, the bit in the register LATCH will not be cleared. The register LATCH will only be cleared if the CPU explicitly clears it by writing a 1 to the bit to be cleared. This means the register LATCH will not be affected by a PINx.DETECT signal being set low.

The LATCH register has split security. Non-secure code can only read the state of the non-secure pins, while the secure pins read as 0. Secure code is able to read the state of all pins.

The LDETECT signal will be set high when one or more bits in the register LATCH 1. The LDETECT signal will be set low when all bits in the register LATCH are successfully cleared to 0.

If one or more bits in the register LATCH are 1 after the CPU has performed a clear operation, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior.

LDETECT is enabled using the DETECTMODE register. See GPIO port and the GPIO pin details.

The following figure illustrates the DETECT signal behavior for these two alternatives.

The device power domains have their own GPIO ports with different capabilities.

The following is a list of all GPIO ports (P[n]) in the system.

• P0 low-power domain – These I/O pins can wake the system up from System OFF or System ON sleep, and can be accessed by all peripherals in the low-power domain.
• P1 and P3 peripheral domain – These I/O pins can wake the system up from System OFF or System ON sleep, and can be accessed by all peripherals in the peripheral domain.
• P2 MCU domain – These I/O pins are faster and can be used for high-speed signals such as trace or fast serial peripheral communication. GPIO P2 cannot wake the system from sleep. P2 does not have the GPIO SENSE or DETECT mechanism, or GPIOTE.

Peripherals cannot mix pins from different ports. All pins must be on the same port.

The following table lists the port special functions and characteristics.

Please note that certain peripherals can operate the GPIOs at higher frequencies than those specified in the table above. In addition to the capabilities of the port, some specific pins have additional functions. These are listed in Pin assignments.

System GPIO pins can be allocated to peripherals with dedicated pins or subsystems such as trace and debug.

The pins of the system are listed in Pin assignments.

By default, all pins are assigned to GPIO or peripherals with PSEL registers. This is the default value of the CTRLSEL value in register PIN_CNF[n] (n=0..31) (Retained).

To allocate a pin to a peripheral or subsystem with dedicated pins, such as GRTC or TND, change the CTRLSEL value in register PIN_CNF[n] (n=0..31) (Retained) for that pin. This will connect the pin to the subsystem or peripheral.

Only the peripheral or subsystem where the pin was allocated can observe and control that pin's state. Reading a pin that is not allocated to the current subsystem will return zero, and writes will be ignored. If a pin is allocated to a subsystem that cannot access it, the pin stays under control of the GPIO peripheral.

When CTRLSEL is used to allocate a peripheral or subsystem, reading the GPIO peripheral registers will not reveal the state of the pins.

The following figure illustrates how to assign a pin to a peripheral that has dedicated pins, or a subsystem such as trace and debug.

For details on pin security, see Security.

The device has dedicated clock pins. Some peripherals, such as SPI, TWI, and TRACE, have clock signals.

The dedicated clock pins are optimized to ensure correct timing between the clock and data signals for these peripherals. All peripherals that have clock signals must use these pins. See Pin assignments for the full list.

The data signal associated with the peripheral must use pins close to the clock pin. This ensures that the internal paths from the peripheral to the pin have the same delay, so that the data and clock signals reach the pins at the same time.

For high-speed signals, the printed circuit board (PCB) layout must use short PCB traces of identical length. This reduces delays and ensures the same delay on the clock and data path.

GPIOHSPADCTRL.BIAS.HSBIAS configures the slew rate of the GPIO pins on P2 in the E0 and E1 drive mode.

A higher slew rate is mandatory for fast signal switching and timing accuracy, helping to maintain correct data transfer at higher speeds. A lower slew rate helps minimize EMI, signal overshoot, and noise.

The recommended setting is to always use the highest slew rate.

Once nRESET is deasserted (rising edge), all GPIOs transition to the high impedance state until device firmware configures them.

When GPIO pins are in a high-impedance state for a prolonged period, external circuits that depend on a clearly defined logic level (either high or low) might require the use of external pull-up or pull-down resistors to ensure reliable operation. However, in most cases this is not required, as the duration of the high-impedance state during the reset cycle is typically very short.