PDM — Pulse density modulation interface

The PDM clock frequency is adjusted through the PRESCALER register in the master clock. The master clock generator does not add jitter to the selected HFCLK source. It is recommended (but not mandatory) to use the crystal as HFCLK source.

By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, and bits for the right are sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital filter which converts the PDM stream into 16-bit PCM samples, then filters and down-samples them to reach the appropriate sample rate.

The EDGE field in the MODE register allows swapping left and right channels, so that left will be sampled on rising edge, and right on falling.

The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM. Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains alternating left and right 16-bit samples (Stereo), or only a left (or only right, depending on the value of the EDGE field) 16-bit samples (Mono). To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination address pointer as the previous buffer is filled.

The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes effective after the current frame has finished transferring, which will generate the STOPPED event. The STOPPED event indicates that all activity in the module is finished, and that the data is available in RAM (EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event may result in unpredictable behavior.

In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in the PDM peripheral.

The filter input is a two-channel PDM serial stream (with left channel on clock high, right channel on clock low). Output consists of two 16-bit PCM samples at a sample rate lower than the PDM clock rate and a ratio defined by the RATIO register.

A digital volume control is implemented within the filter stage of each channel. It can attenuate or amplify the output samples in a range of ±20 dB of the default (reset) setting and is defined by G_PDM,default = 0 dB. The gain is controlled by the GAINL and GAINR registers. As shown in #concept_eqb_fw2_yr__section_vqt_d1g_xcc, depending on OSR value, internal compensation is added for fixed predefined OSR values and a programmable one is available for custom OSR values.

Samples are written directly to RAM, meaning EasyDMA must be configured appropriately.

The address pointer for the EasyDMA channel is set in the SAMPLE.PTR register. If the destination address set in SAMPLE.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about memory regions.

DMA transfer supports Stereo (left and right 16-bit samples) and Mono (left only) data transfer as configured in the OPERATION field of the MODE register. The samples are stored as little endian.

The destination buffer in RAM consists of one block, where the size of the block is set in the SAMPLE.MAXCNT register. The sample format is number of bytes used by the samples that will be stored in the memory. The physical RAM allocated is always the following:

(RAM allocation, in bytes)=SAMPLE.MAXCNT * 2;

Sample mapping depends on MODE.OPERATION.

If OPERATION=Stereo, RAM will contain a succession of left and right samples.

If OPERATION=Mono, RAM will contain a succession of left only samples.

For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as compared to the mono sampling time.

The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT registers have been written. When PDM starts, it will take some time (t_PDM,DATA) for the filters to generate valid data. Transients from the PDM microphone itself may also occur. The first few samples (typically around 50) can contain invalid values or transients. It is advised to discard the first few samples after a PDM start.

As soon as the STARTED event is received, the firmware can write the next SAMPLE.PTR value (this register is double-buffered), to ensure continuous operation.

When the buffer in RAM is full of samples, an END event is triggered. The firmware can start processing the data in the buffer. At the same time, PDM starts acquiring data into the new buffer pointed to by SAMPLE.PTR. It sends a new STARTED event, so that the firmware can update SAMPLE.PTR to the next buffer address.

PDM can be configured with a single microphone (mono), or with two microphones.

When a single microphone is used, connect the microphone clock to CLK, and data to DIN. The following figures show a single PDM microphone wired as left.

The following figures show a single PDM microphone wired as right.

A single microphone (mono) configuration, depending on the microphone’s implementation, either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable data.

If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or to GND on the respective microphone). It is strongly recommended to use two identical microphones so their timing in left and right operations match.

The CLK and DIN signals assigned to the PDM peripheral are mapped to physical pins according to the configuration specified in the PSEL.CLK and PSEL.DIN registers respectively. If the CONNECT field in any PSEL register is set to Disconnected, the associated PDM signal will not be connected to the required physical pins and will not operate properly.

The PSEL.CLK and PSEL.DIN registers and their configurations are only used when PDM is enabled, and retained while the device is in System ON mode. See POWER — Power control for more information about power modes. When the peripheral is disabled, the pins behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register.

To ensure correct behavior in the PDM module, the pins used by the PDM module must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral before enabling the PDM module. This is to ensure that the pins used by the PDM module are driven correctly if the PDM module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected I/Os as long as the PDM module is supposed to be connected to an external PDM circuit.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.