SAADC — Successive approximation analog-to-digital converter

The SAADC peripheral can coexist with COMP and other peripherals using one of AIN[0..7] , provided these are assigned to different pins.

It is not recommended to select the same analog input pin for both peripherals.

The SAADC peripheral supports up to eight external analog inputs. It can be operated in one-shot mode with sampling under software control, or continuous mode with a programmable sampling rate.

Oversampling can be done with either noise shaping or by accumulation and averaging.

Internally, the ADC is always a differential analog-to-digital converter. By default, it is configured with single-ended input in the register CH[n].CONFIG using the MODE field. In single-ended mode, the negative input will be shorted to ground internally.

In single-ended mode, the ADC internal ground is the same as the external ground that is used for measuring the reference voltage. Because of this, the ADC is sensitive to ground bounce on the PCB in single-ended mode. Differential measurement is recommended if this is of concern.

ADC output depends on the settings in the registers CH[n].CONFIG and RESOLUTION registers as follows:

RESULT=[V(P) – V(N) ] * GAIN/REFERENCE * 2(RESOLUTION - m)

V(P) = voltage at input P, 
V(N) = voltage at input N, 
GAIN = the selected gain setting 
m = the mode setting (use m=0 if CONFIG.MODE=SE, or m=1 if CONFIG.MODE=Diff)
REFERENCE = selected reference voltage

The result generated by the ADC will deviate from what is expected due to DC errors like offset, gain, differential non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors due to high source impedance and sampling jitter. For battery measurement, the DC errors are most noticeable.

The ADC has a wide selection of gains controlled in the GAIN field of the register CH[n].CONFIG. If CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.9 V differentially, and the input must be scaled accordingly with proper gain setting.

The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, it is recommended to run CALIBRATEOFFSET at regular intervals. The CALIBRATEDONE event will be generated when the calibration has been completed. The DONE and RESULTDONE events will also be generated.

Up to eight analog input channels, CH[n](n=0..7), can be configured.

See Shared resources for shared input with comparators.

For the SAADC peripheral to operate in one-shot mode, any available channel can be enabled. If more than one CH[n] is configured, SAADC enters scan mode.

An analog input is selected as a positive converter input and enabled by setting register CH[n].PSELP.

An analog input is selected as a negative converter input if register CH[n].PSELN is set. The register CH[n].PSELN will have no effect unless differential mode is enabled and CH[n].PSELP is set, see MODE field in register CH[n].CONFIG.

The SAADC input configuration supports several modes of sampling.

• One-shot, one channel
• One-shot, scan (one sample for each channel)
• Continuous, one channel
• Continuous, scan

Perform the following steps to sample ADC. At least one channel must be enabled in the register CH[n].CONFIG.

1. Enable ADC with register ENABLE.
2. Start ADC using the START task.
3. Trigger the SAMPLE task to sample ADC.

ADC indicates a single ongoing conversion via the register STATUS. Multiple conversions occur in the ADC during oversampling, noise shaping, scan mode, or continuous modes. As a result, the value in register STATUS will toggle at the end of each single conversion.

One-shot mode is configured by enabling only one of the available channels defined in registers CH[n].PSELP, CH[n].PSELN, and CH[n].CONFIG.

After receiving a SAMPLE task, ADC powers up and starts to sample the input voltage. The CH[n].CONFIG.TACQ controls the acquisition time.

The time it takes to perform the first sample is given by the following equation:

 tPWRUP + tACQ + tCONV

tACQ = the acquisition time 
tCONV = the conversion time
tPWRUP = the time it takes to power up ADC

If multiple samples are taken, some combinations of t_ACQ and t_CONV will allow ADC to pipeline sampling and conversion. When this happens, the actual sampling time is t_CONV.

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Both events may occur before the actual value has been transferred into RAM by EasyDMA. For more information, see EasyDMA.

Continuous sampling is achieved by using the internal timer in the ADC, or triggering the SAMPLE task from one of the general purpose timers through the PPI system.

tSAMPLE > tACQ + tCONV

tACQ=0
tCONV=0

tSAMPLE=tPWRUP + tACQ + tCONV

fSAMPLE=1/(tCONV)

The register SAMPLERATE can be used as a local timer instead of triggering individual SAMPLE tasks. When SAMPLERATE.MODE is set to Timers, it is sufficient to trigger SAMPLE task only once in order to start the SAADC peripheral. Triggering the STOP task will stop sampling. The SAMPLERATE.CC field controls the sample rate.

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Both events may occur before the value has been transferred into RAM by EasyDMA.

SAADC has multiple options to improve sample accuracy. Noise shaping modes provide the highest performance by enabling a delta-sigma configuration with analog filtering, oversampling, and digital filtering. Pure oversampling is also supported.

A channel is considered enabled if CH[n].PSELP is set. If more than one channel is enabled, SAADC enters scan mode.

In scan mode, one SAMPLE task will trigger one conversion per enabled channel. The time it takes to sample all channels is calculated by the following:

Total time < Sum(CH[x].tACQ+tCONV), x=0..enabled channels

A DONE event signals that one channel has been sampled.

In this mode, the RESULTDONE event is generated after each sample, once for each channel.

After configuring RESULT.PTR and RESULT.MAXCNT, SAADC resources are started by triggering the START task. SAADC uses EasyDMA to store results in a Result buffer in RAM.

The Result buffer is located at the address specified in the RESULT.PTR register. The RESULT.PTR register is double-buffered and can be updated and prepared for the next START task immediately after the STARTED event is generated. The size of the Result buffer (in bytes) is specified in the RESULT.MAXCNT register, and SAADC will generate an END event when the Result buffer is full, see SAADC. Results are stored in little-endian byte order in Data RAM. Every sample will be sign extended to 16 bits before stored in the Result buffer.

SAADC is stopped by triggering the STOP task. The STOP task will terminate an ongoing sampling. SAADC will generate a STOPPED event when it has stopped. If SAADC has already stopped when the STOP task is triggered, the STOPPED event is still generated.

If the RESULT.PTR is not pointing to a RAM region accessible from the peripheral, an EasyDMA transfer may result in a HardFault, memory corruption, or both. See Memory for more information about the memory regions.

The EasyDMA will have finished accessing the RAM when the END or STOPPED event has been generated.

The RESULT.AMOUNT register can be read following an END event or a STOPPED event to see how many bytes have been transferred to the Result buffer in RAM from when the START task was triggered.

In scan mode, SAMPLE tasks can be triggered once the START task is triggered. The END event is generated when the number of samples transferred to memory reaches the value specified by RESULT.MAXCNT. After an END event, the START task needs to be triggered again before new samples can be taken. For more information about the scan mode, see Scan mode.

SAADC can use different reference voltages (VREF), controlled in the REFSEL field of the register CH[n].CONFIG.

The accepted VREF voltages are the following:

• Internal reference, VREF=0.9 V
• External reference, VREF provided by the EXTREF pin

ADC is preceded by a gain stage which has a programmable gain. The voltage range seen at the input of the gain stage is the following:

VRangeDifferential=±VREF/GAIN

VRangeSingleEnded=±0.5*VREF/GAIN

The AIN[0..7] inputs cannot exceed VDD, or be lower than VSS. The input ranges are also limited by the REFERENCE and GAIN used.

The following condition must always hold true for valid measurements, otherwise the ADC will saturate and report the max value determined by the RESOLUTION.

 [V(P) - V(N) ] * GAIN/REFERENCE ≤ 1 

To sample the input voltage, the SAADC peripheral connects a capacitor to the input.

The acquisition time indicates how long the capacitor is connected, see the TACQ field in the register CH[n].CONFIG. The required acquisition time depends on the source (R_source) resistance. For high source resistance, the acquisition time should be increased, see Acquisition time.

Monitoring a channel with an event can be set up by configuring limit register CH[n].LIMIT.

If the conversion result is higher than the defined high limit, or lower than the defined low limit, the appropriate event will be generated. Limit comparison happens automatically and does not need to be enabled.

When setting the channel limits, CH[n].LIMIT.HIGH must be higher than, or equal to, CH[n].LIMIT.LOW. In other words, an event can only be generated when the input signal has been sampled outside of the defined limits. It is not possible to generate an event when the input signal is inside a defined range by switching high and low limits.

If a channel does not require comparison, software ignores the related events. In that situation, the value of the limits registers is irrelevant, so it does not matter if CH[n].LIMIT.LOW is lower than CH[n].LIMIT.HIGH or not.

Clock jitter can affect sample timing accuracy and circuit noise can affect ADC performance.

Jitter can be between START tasks or from START task to acquisition. START timer accuracy and regulator start up times and references will contribute to variability. Sources of circuit noise may include CPU activity and the DC/DC regulator. Best ADC performance is achieved using START timing based on the TIMER module, HFXO clock source, and Constant Latency mode.