TDM — Time division multiplexed audio interface

The TDM interface is comprised of a frame synchronization pulse (FSYNC), a serial clock (SCLK), and the serial audio data (SDIN or SDOUT).

The Master always supplies the clock signals FSYNC and SCK to the Slave. Serial data can be received on the input data pin SDIN, or transmitted on the output data pin SDOUT.

TDM supports both transmission (TX) and reception (RX) of serial data. In both cases the serial data is shifted synchronously to the SCK clock signal.

TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on the rising edge of SCK. To change the active edge of SCK, use register CONFIG.SCK.POLARITY.

The most significant bit (MSB) is always transmitted first.

TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in CONFIG.RXTXEN.

Transmission and/or reception is started by triggering the START task. When transmission is enabled in CONFIG.TXEN), the TXPTRUPD event will be generated for every number of transmitted data words given by TXD.MAXCNT. Each data word contains one or more samples. The TXPTRUPD event is generated just before MAXCNT number of bytes have been transmitted. Similarly, when reception is enabled in CONFIG.RXTXEN, the RXPTRUPD event is generated just after MAXCNT number of bytes have been received.

If transmitting more samples than receiving (TXD.MAXCNT is larger than RXD.MAXCNT), the additional received samples will be discarded.

During receive-only operation, once RXD.MAXCNT bytes have been received, any further samples are discarded.

CONFIG.ORS follows the layout of a 32-bit memory word and can contain four 8-bit samples, two 16-bit samples, one right-aligned 24-bit sample sign-extended to 32 bit, or one 32-bit sample. The size of the samples is dependent on CONFIG.SWIDTH. For details on the memory word layout, see Channel mask and EasyDMA.

The MAXCNT event is generated synchronously to the active FSYNC edge at the beginning of a frame after transmitting RXD.MAXCNT bytes. The initial MAXCNT event is generated at the first active edge of FSYNC after the START task has been triggered. The MAXCNT event is generated once all data has been transmitted and/or received. The data will be available in RAM upon completion of the EasyDMA operation.

Transmission can be aborted by using the ABORT task. This will abort TDM transfer possibly without completing MAXCNT words, and will cause the ABORTED event to be generated.

In addition to the frame sync (FSYNC) pulse, TDM has two clock signals. The master clock MCK and the sample data bit clock SCK.

MCK and SCK are independent and can be configured individually.

The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being transferred on the serial data lines SDIN and SDOUT.

The polarity of SCK is configured in CONFIG.SCK.POLARITY.

When operating in Master mode, SCK clock source and frequency and is configured in CONFIG.SCK.SRC and CONFIG.SCK.DIV respectively. For CONFIG.SCK.DIV value, see Clock divider equations.

When operating in Slave mode, SCK is an input signal provided by the external master.

The optional master clock (MCK) is independent from SCK and FSYNC.

The master clock generator is enabled/disabled using CONFIG.MCK.EN, and the generator is started or stopped by the START or STOP tasks respectively.

FSYNC defines the start of the frame in the serial bit streams sent and received on SDOUT and SDIN, respectively. It is often referred to as "word clock", "sample clock", "word select", "frame clock", or "left/right clock".

In master mode, FSYNC duration is configured in CONFIG.FSYNC.DURATION. The duration can either be one SCK period, or one channel. This is illustrated in the following figure.

Regardless of FSYNC duration, the frequency of FSYNC is equivalent to the audio sample rate.

If is possible to configure the sample size to only use a fraction of a channel, see Width and alignment. Also in this configuration FSYNC duration is the channel width (not the audio sample size), as illustrated in the following figure.

The alignment of the frame with the active edge of FSYNC can be adjusted using the register CONFIG.CHANNEL.DELAY. This allows the data to be delayed one or more periods of the serial clock following the active edge of FSYNC, as illustrated in the following figure.

When TDM is configured for the I²S mode, each frame contains one left and right sample pair, with the left sample being transferred during the low half period of FSYNC followed by the right sample being transferred during the high half period of FSYNC. There is a single SCK clock pulse delay between FSYNC edge and the first bit of the sample.

With the Aligned format, each frame contains one left and right sample pair, with the left sample being transferred during the high half period of FSYNC followed by the right sample being transferred during the low half period of FSYNC. There is no delay between FSYNC edge and the first bit of the sample.

For TDM, the active edge of FSYNC defines the beginning of a frame. The words within the frame are transferred continously, with no transitions of FSYNC.

The clock source for SCK and MCK is selectable in registers CONFIG.MCK.SRC and CONFIG.SCK.SRC respectively.

The following clocks can be selected as the clock source.

• Peripheral clock (PCLK)
• Additional clock (ACLK)

To improve the clock accuracy and jitter performance, it is recommended (but not mandatory) that the PCLK source used is running off the external crystal. The ACLK source requires the use of a crystal. See CLOCK — Clock control for more information about clock sources.

The clock generator can be bypassed so that MCK or SCK is derived directly from the input source. This can be configured in the BYPASS field of their respective registers CONFIG.SCK.SRC and CONFIG.SCK.SRC.

MCK and SCK frequency can be adjusted on-the-fly by using CONFIG.MCK.DIV or CONFIG.SCK.DIV.

The following equations are used to select SCK and MCK frequencies.

The first equation is used to calculate the value of CONFIG.MCK.DIV or CONFIG.SCK.DIV for a given source, and MCK or SCK frequency.

Because of rounding errors, an accurate MCK clock may not be achievable. The equation does not take into account the maximum register values of CONFIG.MCK.DIV or CONFIG.SCK.DIV.

The actual MCK or SCK frequency can be calculated using the equation below.

The clock error can be calculated using the equation below. The error e is the percentage difference from the requested f_MCK or f_SCK frequency.

Each audio data sample is followed by sufficient number of zero data bits to complete an M-bit word. The CONFIG.SWIDTH register defines the sample width of the data read and written to memory, as well as the number of SCK clock cycles per word. The M-bit word is sometimes referred to as a channel block.

The following figure illustrates a configuration with identical sample and channel/word widths. The number of SCK pulses matches the number of sample bits.

The next figure illustrates a configuration with greater word width than sample width. The number of SCK pulses are greater than the number of sample bits, with the sample being left-aligned in the word.

Alignment of samples

If the word width differs from the sample width, the sample value can be either right or left-aligned inside a word, as specified in CONFIG.ALIGN.

When using left-alignment, each word starts with the MSB of the sample value, as illustrated in the following figure.

When using right-alignment, each word ends with the LSB of the sample value. This is illustrated in the following figure.

TDM implements EasyDMA for accessing RAM without CPU intervention.

Channel masking

Channel masking takes place between the transceiver and the EasyDMA access to memory as illustrated in the following figure.

Which of the samples transferred over the data lines are accessed by EasyDMA, is selected by the register CONFIG.CHANNEL.MASK. In this register, channels are enabled or disabled from the memory transfers. Disabled channels are ignored - transmitted bits are zero, and received data is discarded. Enabled channels will have their data stored to, or received from, memory.

Memory map for single channel (mono)

When the resulting data after channel masking is a single channel, the following figures show how this channel's samples are mapped to memory. The mapping is valid for both RX and TX.

Memory map for two channels (stereo)

When the resulting data after channel masking is two channels (stereo), the following figures show how this channel's samples are mapped to memory. The mapping is valid for both RX and TX.

Memory map for multi-channel (three or more)

The following equation can be used to calculate the address of the word storing a multi-channel sample. The equation is valid for both RX and TX. The following notation is used.

• S is the number of data bits in a sample
• N total number of channels per sample
• n is the channel number of the current sample
• m is the sample number

When the resulting data after channel masking is three or more the samples are stored sequentially in memory, similar to stereo. The following figures show how the samples are mapped to memory. The mapping is valid for both RX and TX.

The MCK, SCK, FSYNC, SDIN and SDOUT signals associated with TDM are mapped to physical pins according to the pin numbers specified in the PSEL.x registers.

These pins are acquired whenever TDM is enabled through the register ENABLE.

When a pin is acquired by TDM, the direction of the pin (input or output) will be configured automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for the various TDM pins are shown in the following tables.

To secure correct signal levels on the pins in System OFF mode, and when TDM is disabled, these pins must be configured in the GPIO peripheral directly.