USBHS — Universal Serial Bus High Speed

RW

PLLITUNE

[0x0..0x3]

PLL Integral Path Tune

RW

PLLPTUNE

[0x0..0xf]

PLL Proportional Path Tune

RW

COMPDISTUNE0

[0x0..0x7]

Disconnect Threshold Adjustment

RW

SQRXTUNE0

[0x0..0x3]

Squelch Threshold Adjustment

RW

VDATREFTUNE0

[0x0..0x3]

Data Detect Voltage Adjustment

RW

TXHSXVTUNE0

[0x0..0x2]

Transmitter High-Speed Crossover Adjustment

RW

TXFSLSTUNE0

[0x0..0x7]

FS/LS Source Impedance Adjustment

RW

TXVREFTUNE0

[0x0..0x7]

HS DC Voltage Level Adjustment

RW

TXRISETUNE0

[0x0..0x2]

HS Transmitter Rise/Fall Time Adjustment

RW

TXRESTUNE0

[0x0..0x2]

USB Source Impedance Adjustment

RW

TXPREEMPAMPTUNE0

[0x0..0x2]

HS Transmitter Pre-Emphasis Current Control

RW

TXPREEMPPULSETUNE0

[0x0..0x1]

HS Transmitter Pre-Emphasis Duration Control

RW

FSEL

Select reference clock frequency

RW

PLLBTUNE

PLL bandwidth adjustment

RW

COMMONONN

Common block power down control

RW

OPMODE0

RW

XCVRSEL0

RW

DPPULLDOWN

RW

DMPULLDOWN

RW

SUSPENDM0

RW

VBUSVALID

RW

ID

Overrides OTG ID pin signal

RW

OPMODE0

RW

XCVRSEL0

RW

DPPULLDOWN

This field controls the pull-down resistor on D+

RW

DMPULLDOWN

This field controls the pull-down resistor on D-

RW

SUSPENDM0

RW

VBUSVALID

Signals to the PHY that VBUS is valid, and enables the pull-up resistor on D+

This field is not functional in Host mode.

RW

ID

Overrides OTG ID pin signal

RW

VBVALIDOVEN

Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn)

This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.VbvalidOvVal.

RW

VBVALIDOVVAL

Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal)

This bit is used to set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn is set.

RW

AVALIDOVEN

Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn)

This bit is used to enable/disable the software to override the Avalid signal using the GOTGCTL.AvalidOvVal.

RW

AVALIDOVVAL

Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal)

This bit is used to set Override value for Avalid signal when GOTGCTL.AvalidOvEn is set.

RW

BVALIDOVEN

Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn)

This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.BvalidOvVal.

RW

BVALIDOVVAL

Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal)

This bit is used to set Override value for Bvalid signal when GOTGCTL.BvalidOvEn is set.

RW

DBNCEFLTRBYPASS

Mode: Host and Device. Debounce Filter Bypass

Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when enabled. Note: This register bit is valid only when debounce filters are present in core.

R

CONIDSTS

Mode: Host and Device. Connector ID Status (ConIDSts)

Indicates the connector ID status on a connect event. Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later. Reset: - 1'b0: in host only mode (OTG_MODE = 5 or 6) - 1'b1: in all other configurations

R

DBNCTIME

Mode: Host only. Long/Short Debounce Time (DbncTime)

Indicates the debounce time of a detected connection.

R

ASESVLD

Mode: Host only. A-Session Valid (ASesVld)

Indicates the Host mode transceiver status. Note: If you do not enabled OTG features (such as SRP and HNP), the read reset value will be 1. The vbus assigns the values internally for non-SRP or non-HNP configurations. In case of OTG_MODE=0, the reset value of this bit is 1'b0.

R

BSESVLD

Mode: Device only. B-Session Valid (BSesVld)

Indicates the Device mode transceiver status. In OTG mode, you can use this bit to determine if the device is connected or disconnected. Note: - If you do not enable OTG features (such as SRP and HNP), the read reset value will be 1.The vbus assigns the values internally for non- SRP or non-HNP configurations. - In case of OTG_MODE=0, the reset value of this bit is 1'b0. - The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.

RW

OTGVER

OTG Version (OTGVer)

Indicates the OTG revision.

R

CURMOD

Current Mode of Operation (CurMod)

Mode: Host and Device Indicates the current mode. Reset: Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.

R

MULTVALIDBC

Mode: Host and Device. Multi Valued ID pin (MultValIdBC)

Battery Charger ACA inputs in the following order:

RW

CHIRPEN

Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending an actual Chirp "K" signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always operates at High Speed and High speed chirp is not used

RW

EUSB2PHYDISCSUPP

This field is only applicable to Device mode and must be set to 1'b1 if eUSB2 PHY is used.

RW

SESENDDET

Mode: Host and Device. Session End Detected (SesEndDet)

The controller sets this bit when the utmiotg_bvalid signal is deasserted. This bit can be set only by the core and the application must write 1 to clear it.

RW

SESREQSUCSTSCHNG

Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng)

The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit in the OTG Control and Status register (GOTGCTL.SesReqScs) to check for success or failure. This bit can be set only by the core and the application must write 1 to clear it.

RW

HSTNEGSUCSTSCHNG

Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng)

The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation Success bit of the OTG Control and Status register (GOTGCTL.HstNegScs) to check for success or failure. This bit can be set only by the core and the application must write 1 to clear it.

RW

HSTNEGDET

Mode:Host and Device. Host Negotiation Detected (HstNegDet)

The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the application must write 1 to clear it.

RW

ADEVTOUTCHG

Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg)

The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect.This bit can be set only by the core and the application must write 1 to clear it.

RW

DBNCEDONE

Mode: Host only. Debounce Done (DbnceDone)

The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). This bit can be set only by the core and the application must write 1 to clear it.

RW

MULTVALIPCHNG

This bit when set indicates that there is a change in the value of at least one ACA pin value.

This bit is present only if OTG_BC_SUPPORT=1, otherwise it is reserved.

RW

GLBLINTRMSK

Mode: Host and device. Global Interrupt Mask (GlblIntrMsk)

The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the controller.

RW

HBSTLEN

Mode: Host and device. Burst Length/Type (HBstLen)

This field is used in both External and Internal DMA modes. In External DMA mode, these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper to interface the External DMA Controller interface to Synopsys DW_ahb_dmac or ARM PrimeCell. External DMA Mode defines the DMA burst length in terms of 32-bit words: Internal DMA Mode AHB Requester burst type:

RW

DMAEN

Mode: Host and device. DMA Enable (DMAEn)

This bit is always 0 when Completer-Only mode has been selected.

RW

NPTXFEMPLVL

Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)

This bit is used only in Completer mode. In host mode and with Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered. Host mode and with Shared FIFO with device mode: Dedicated FIFO in device mode:

RW

PTXFEMPLVL

Mode: Host only. Periodic TxFIFO Empty Level (PTxFEmpLvl)

Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Completer mode.

RW

REMMEMSUPP

Mode: Host and Device. Remote Memory Support (RemMemSupp)

This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers. - GAHBCFG.RemMemSupp=1 The int_dma_req output signal is asserted when the DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from the controller. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint. - GAHBCFG.RemMemSupp=0 The int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the Core Boundary and it does not wait for the sys_dma_done signal to complete the DATA transfers.

RW

NOTIALLDMAWRIT

Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit)

This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1. - GAHBCFG.NotiAllDmaWrit = 1 The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint. - GAHBCFG.NotiAllDmaWrit = 0 The core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.

RW

AHBSINGLE

Mode: Host and Device. AHB Single Support (AHBSingle)

This bit when programmed supports Single transfers for the remaining data in a transfer when the core is operating in DMA mode. Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR burst type. Enable this feature when the AHB Completer connected to the core does not support INCR burst (and when Split, and Retry transactions are not being used in the bus).

RW

LOAEOPCHECKCLKSBYTE

Mode: Host. Number of clock cycles to check for EOP SE0 for LOA logic

Note: - This field only affects USB2.0 FS operation in UTMI 8bit mode. The mac_prt logic checks for the programmed number of clocks of SE0 to validate an EOP for a packet. - The actual number of clocks checked will be the value programmed plus 1. So a value 1 results in checking for 2 clocks of SE0. Value of 3 checks 4 clocks of SE0 and so on. - The default value is 1, which results in 2 clocks of SE0 check.

RW

LOAEOPCHECKCLKSWORD

Mode: Host. Number of clock cycles to check for EOP SE0 for LOA logic

Note: - This field only affects USB2.0 FS operation in UTMI 16bit mode. The mac_prt logic checks for the programmed number of clocks of SE0 to validate an EOP for a packet. - The actual number of clocks checked will be the value programmed plus 1. So a value 1 results in checking for 2 clocks of SE0. Value of 3 checks 4 clocks of SE0 and so on. - The default value is 1, which results in 2 clocks of SE0 check.

RW

TOUTCAL

Mode: Host and Device. HS/FS Timeout Calibration (TOutCal)

The number of PHY clocks that the application programs in this field is added to the high-speed/full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the linestate condition can vary from one PHY to another. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock are as follows: High-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times

RW

PHYIF

Mode: Host and Device. PHY Interface (PHYIf)

The application uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is chosen, this must be Set to 8-bit mode. This bit is writable only If UTMI+ and ULPI were selected. Otherwise, this bit returns the value for the power-on interface selected during configuration.

R

ULPIUTMISEL

Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel)

The application uses this bit to select either a UTMI+ interface or ULPI Interface.

R

FSINTF

Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf)

The application uses this bit to select either a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface. If a USB 1.1 Full-Speed Serial Transceiver interface was not selected, this bit is always 0, with Write Only access. If a USB 1.1 FS interface was selected, Then the application can Set this bit to select between the 3- and 6-pin interfaces, and access is Read and Write. Note: For supporting the new 4-pin bi-directional interface, you need to select 6-pin unidirectional FS serial mode, and add an external control to convert it to a 4-pin interface.

R

PHYSEL

PHYSel

Mode: Host and Device USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select (PHYSel) The application uses this bit to select either a high-speed UTMI+ or ULPI PHY, or a full-speed transceiver. If a USB 1.1 Full-Speed Serial Transceiver interface was not selected in, this bit is always 0, with Write Only access. If a high-speed PHY interface was not selected in, this bit is always 1, with Write Only access. If both interface types were selected (parameters have non-zero values), the application uses this bit to select which interface is active, and access is Read and Write.

RW

USBTRDTIM

Mode: Device only. USB Turnaround Time (USBTrdTim)

Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). This must be programmed to Note:Refer to Programming Guide Section "Choosing the Value of GUSBCFG.USBTrdTim" for the turnaround time calculation. During the AHB Clock Frequency selection, it is recommended to consider mis-sampling into account for USBTrdTim. USB turnaround time is critical for certification where long cables and 5-Hubs are used. If you need the AHB to run at less than 30 MHz (or less than 42MHz when operating in 16-bit UTMI mode in HS speed), and if USB turnaround time is not critical, these bits can be programmed to a larger value.

RW

PHYLPWRCLKSEL

PHY Low-Power Clock Select (PhyLPwrClkSel)

Mode: Host and Device Selects either 480-MHz or 48-MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power. In 480 MHz mode, the UTMI interface operates at either 60 or 30-MHz, depending upon whether 8- or 16-bit data width is selected. In 48-MHz mode, the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode (depending on the PHY vendor). This bit drives the utmi_fsls_low_power core output signal, and is valid only for UTMI+ PHYs.

RW

TERMSELDLPULSE

Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse)

This bit selects utmi_termselect to drive data line pulse during SRP.

R

ICUSBCAP

Mode: Host and Device. IC_USB-Capable (IC_USBCap)

The application uses this bit to control the core's IC_USB capabilities. This bit is writable only if OTG_ENABLE_IC_USB=1 and OTG_FSPHY_INTERFACE!=0. The reset value depends on the configuration parameter OTG_SELECT_IC_USB when OTG_ENABLE_IC_USB = 1. In all other cases, this bit is set to 1'b0 and the bit is read only.

RW

TXENDDELAY

Mode: Device only. Tx End Delay (TxEndDelay)

Setting this bit to 1'b1 enables the controller to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup. The default value of this field is 1'b1 and it is not recommended to program it to 1'b0. The option to set it to 1'b0 (Normal Mode) is present only for debug purpose.

RW

FORCEHSTMODE

Mode: Host and device. Force Host Mode (ForceHstMode)

Writing a 1 to this bit forces the core to host mode irrespective of utmiotg_iddig input pin. After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.

RW

FORCEDEVMODE

Mode:Host and device. Force Device Mode (ForceDevMode)

Writing a 1 to this bit forces the controller to device mode irrespective of utmiotg_iddig input pin. After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.

W

CORRUPTTXPKT

Mode: Host and device. Corrupt Tx packet (CorruptTxPkt)

This bit is for debug purposes only. Never Set this bit to 1. The application must always write 1'b0 to this bit.

RW

CSFTRST

Mode: Host and Device. Core Soft Reset (CSftRst)

Resets the hclk and phy_clock domains as follows: - Clears the interrupts and all the CSR registers except the following register bits: -- PCGCCTL.RstPdwnModule -- PCGCCTL.GateHclk -- PCGCCTL.PwrClmp -- PCGCCTL.StopPPhyLPwrClkSelclk -- GUSBCFG.ForceDevMode -- GUSBCFG.ForceHstMode -- GUSBCFG.PhyLPwrClkSel -- GUSBCFG.DDRSel -- GUSBCFG.PHYSel -- GUSBCFG.FSIntf -- GUSBCFG.ULPI_UTMI_Sel -- GUSBCFG.PHYIf -- GUSBCFG.TxEndDelay -- GUSBCFG.TermSelDLPulse -- GUSBCFG.ULPIClkSusM -- GUSBCFG.ULPIAutoRes -- GUSBCFG.ULPIFsLs -- GGPIO -- GPWRDN -- GADPCTL -- HCFG.FSLSPclkSel -- DCFG.DevSpd -- DCTL.SftDiscon - All module state machines - All module state machines (except the AHB Completer Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed. - Any transactions on the AHB Requester are terminated as soon as possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. - When Hibernation or ADP feature is enabled, the PMU module is not reset by the Core Soft Reset. The application can write to this bit any time it wants to reset the core. The application must clear this bit after checking the bit 29 of this register (Core Soft Reset Done). Software must also must check that bit 31 of this register is 1 (AHB Requester is IDLE) before starting any operation. Typically software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation.

RW

PIUFSSFTRST

Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)

Resets the PIU FS Dedicated Controller All module state machines in FS Dedicated Controller of PIU are reset to the IDLE state. Used to reset the FS Dedicated controller in PIU in case of any PHY Errors like Loss of activity or Babble Error resulting in the PHY remaining in RX state for more than one frame boundary. This is a self clearing bit and core clears this bit after all the necessary logic is reset in the core.

RW

FRMCNTRRST

Mode: Host only. Host Frame Counter Reset (FrmCntrRst)

The application writes this bit to reset the (micro)Frame number counter inside the core. When the (micro)Frame counter is reset, the subsequent SOF sent out by the core has a (micro)Frame number of 0. When application writes 1 to the bit, it might not be able to read back the value as it gets cleared by the core in a few clock cycles.

RW

RXFFLSH

Mode: Host and Device. RxFIFO Flush (RxFFlsh)

The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the controller is neither reading from the RxFIFO nor writing to the RxFIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires eight clocks (slowest of PHY or AHB clock) to clear.

RW

TXFFLSH

Mode: Host and Device. TxFIFO Flush (TxFFlsh)

This bit selectively flushes a single or all transmit FIFOs, but cannot do so If the core is in the midst of a transaction. The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO. Verify using these registers: - ReadNAK Effective Interrupt ensures the core is not reading from the FIFO - WriteGRSTCTL.AHBIdle ensures the core is not writing anything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured or when switching between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk.

RW

TXFNUM

Mode: Host and Device. TxFIFO Number (TxFNum)

This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit. -- Non-periodic TxFIFO flush in Host mode -- Non-periodic TxFIFO flush in device mode when in shared FIFO operation -- Tx FIFO 0 flush in device mode when in dedicated FIFO mode -- Periodic TxFIFO flush in Host mode -- Periodic TxFIFO 1 flush in Device mode when in shared FIFO operation -- TXFIFO 1 flush in device mode when in dedicated FIFO mode -- Periodic TxFIFO 2 flush in Device mode when in shared FIFO operation -- TXFIFO 2 flush in device mode when in dedicated FIFO mode ... -- Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation -- TXFIFO 15 flush in device mode when in dedicated FIFO mode