Trace

The device supports ETM and ITM trace.

Trace data from the ETM and ITM is sent to an external debugger through a 4-bit wide parallel trace port (TPIU), as illustrated in Access port unlocking.

In addition to parallel trace mode, the TPIU supports serial trace mode through the serial wire output (SWO) trace protocol. Parallel and serial trace modes cannot be used at the same time. ETM trace is only supported in parallel trace mode. ITM trace is supported in both parallel and serial trace mode. See the debug documentation of the IDE for more information.

TPIU trace pins are multiplexed with GPIO pins. The SWO and TRACEDATA[0] pins can use the same GPIO. See Pin assignments for more information.

Trace speed is configured in the register TRACEPORTSPEED. Trace pin speed is determined by the GPIO drive setting of the multiplexed pins. See GPIO — General purpose input/output for information on drive settings.

The trace speed must be configured according to the maximum speed of the GPIO pins used for trace. For information about GPIO speed, see GPIO — General purpose input/output.

Enabling the trace port

A specific sequence of operations must be performed to enable the trace port.

Enable trace and debug using the following code.
```
NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
```

Set drive strength to the highest possible value to ensure fast operation. Do this for all trace pins that will be used.

#define TRACE_PIN_CONFIG    ((GPIO_PIN_CNF_DRIVE0_E0 << GPIO_PIN_CNF_DRIVE0_Pos) \
                            | (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_Pos))
#define NRF_Px_S NRF_P2_S // From pin assignments

#define TRACE_PIN_CLEAR     (~(GPIO_PIN_CNF_CTRLSEL_Msk | GPIO_PIN_CNF_DRIVE0_Msk \
                            | GPIO_PIN_CNF_DRIVE1_Msk))

// Clear the bitfields before configuring to make sure the correct value is written.
NRF_Px_S->PIN_CNF[TRACE_TRACECLK_PIN] &= TRACE_PIN_CLEAR;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA0_PIN] &= TRACE_PIN_CLEAR;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA1_PIN] &= TRACE_PIN_CLEAR;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA2_PIN] &= TRACE_PIN_CLEAR;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA3_PIN] &= TRACE_PIN_CLEAR;

NRF_Px_S->PIN_CNF[TRACE_TRACECLK_PIN] |= TRACE_PIN_CONFIG;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA0_PIN] |= TRACE_PIN_CONFIG;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA1_PIN] |= TRACE_PIN_CONFIG;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA2_PIN] |= TRACE_PIN_CONFIG;
NRF_Px_S->PIN_CNF[TRACE_TRACEDATA3_PIN] |= TRACE_PIN_CONFIG;

Trace port speed is configured as a prescaled version of the CPU frequency and must be at least half the CPU frequency to avoid dropping trace packets. The trace speed must also be within the maximum speed of the GPIO pins used for trace. For information about GPIO speed, see GPIO — General purpose input/output.
```
NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV2;
```
Configure Arm CoreSight components. See documentation for Arm CoreSight for more information.