CPU Electrical specification

CPU performance

The CPU performance metrics are derived from benchmarks executed on highly optimized firmware. The firmware is compiled using the specified compiler version and settings to ensure accurate and reliable performance data.

Compiler: Arm version 6.16 (armclang)

Compiler flags:

--target=arm-arm-none-eabi -c -g -masm=auto -Wno-unused-value -mcpu=cortex-m33 -mfloat-abi=hard -mfpu=fpv5-sp-d16 -flto -Omax

Linker flags:

--lto --remove


Symbol	Description	Typ.	Units
CM_RRAMCACHE128	CPU running CoreMark at 128 MHz from RRAM, cache enabled	503	CoreMark
CM_rram128/MHz	CoreMark per MHz, running from RRAM, cache enabled, HFXO128M	3.93	CoreMark/MHz
CM_RAM128	CPU running CoreMark at 128 MHz from RAM	464	CoreMark

CPU wakeup times


Symbol	Description	Typ.	Units
t_R2ON	Time from pin reset to CPU executes the first instruction	44	µs
t_OFF2ON	Time from wake-up from System OFF mode to CPU executes the first instruction	37	µs
t_{IDLE2CPU,POWEROFF}	Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction, RRAMC LOWPOWERCONFIG is using PowerOff mode. CACHE is disabled.	18	µs
t_{IDLE2CPU,CONSTLAT,POWEROFF}	Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction in constant latency sub-mode, RRAMC LOWPOWERCONFIG is using PowerOff mode. CACHE is disabled.	17	µs
t_{IDLE2CPU,CACHE}	Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction. CACHE is enabled.	2	µs
t_{IDLE2CPU,STANDBY}	Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction, RRAMC LOWPOWERCONFIG is using Standby mode. CACHE is disabled.	0.5	µs
t_{IDLE2CPU,CACHE,CONSTLAT}	Wakeup time from CPU sleep (WFI,WFE) to CPU executes the next instruction in constant latency sub-mode, CACHE enabled.	0.3	µs