Address format

Addresses in the system memory map follow the address format described in the following tables.

Table 3. Address regions format
Address bitsDescriptionEnumeration
[28:0]Address space
[31:29]Address regions

0: Program memory

1: Data memory

2: Peripherals/APB space

7: CPU internal peripherals, like Arm Cortex private peripheral bus (PPB)

The program and data memory address format is described in the following table.

Table 4. Program memory and data memory address format
Address bitsDescriptionEnumeration
[23:0]Address space
[28:24]ReservedSet to zero
[31:29]Address regions

0: Program memory

1: Data memory

The peripheral address format is described in the following table.

Table 5. Peripheral address format
Address bitsDescriptionEnumeration
[11:0]Peripheral address space
[17:12]Peripheral subordinate indexUsed for configuring the , as the index n of register SPU.PERIPH[n].PERM.
[20:12]Interrupt vector numberThe index in the interrupt vector table
[23:18]Peripheral APB bus number

1: APB peripherals in MCU power domain

2: APB peripherals in RADIO power domain

3: APB peripherals in PERI power domain

4: APB peripherals in LP power domain

[27:24]ReservedSet to zero
[28]ReservedSet to zero
[31:29]Address regions

2: Peripherals on APB bus