CPU
The Arm® Cortex®-M33 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a super set of 16- and 32-bit instructions to maximize code density and performance.
This processor has the following features that enable energy-efficient arithmetic and high-performance signal processing:
- Hardware divide
- Memory Protection Unit (MPU)
- Stack limit checking
The Arm Cortex® Microcontroller Software Interface Standard (CMSIS) is implemented and available for the processor.
Real-time execution is highly deterministic in Thread mode, to and from sleep modes, and when handling events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).
Instruction cache on the C-bus (code bus) of the Cortex-M33 CPU improves performance when fetching instructions (or data) from internal non-volatile memory. For more information on cache, see CACHE — Instruction/data cache. CPU performance parameters including wait states for configurations, CPU current consumption and efficiency, and processing power and efficiency based on the CoreMark® benchmark can be found in CPU Electrical specification.
CPU and support module configuration
The Arm Cortex®-M33 processor has a number of CPU options and support modules implemented on the device.
| Option | Description | Implemented |
|---|---|---|
| WIC | Wakeup Interrupt Controller | No |
| Endianness | Memory system endianness | Little endian |
| DWT | Data Watchpoint and Trace | Yes |
| Module | Description | Implemented |
|---|---|---|
| MPU | Number of MPU regions | 4 |
| SAU | Number of SAU regions | 0 |
| FPU | Floating-point unit | No |
| DSP | Digital Signal Processing Extension | No |
| Arm TrustZone® for Armv8-M | Armv8-M Security Extensions | No |
| CPIF | Coprocessor interface | No |
| ETM | Embedded Trace Macrocell | No |
| ITM | Instrumentation Trace Macrocell | No |
| MTB | Micro Trace Buffer | No |
| CTI | Cross Trigger Interface | No |
| BPU | Breakpoint Unit | Yes |
| INITVTOR | Initial vector table offset | 0x00000000 |