CACHE — Instruction/data cache

The cache is a direct mapped cache. Both instruction and data accesses towards NVM memory are cached.

The cache has the following features:

4x64-bit cache line
Ability to enable/disable cache at run-time
Writes to cached memory are write-around and invalidate the cache line
Manual invalidation
Performance hit/miss counter registers for profiling CACHE operations

The cache must be enabled by the ENABLE register.

Architecture

The following figure shows the cache architecture.

Cache Overview — Figure 1. Cache overview


Bit	Name	Description
V	Valid	Indicates if a cache entry is valid. All V fields are cleared when enabling the cache, invalidating the cache, or when changing CACHE mode.

Profiling

The cache provides a scoreboard that tracks the hits and misses within the cache.

The results are available through a set of registers that can be used to indicate how well the cache is performing.

Profiling is enabled using PROFILING.ENABLE. All profiling counters can be cleared at any time using PROFILING.CLEAR. After being cleared, the counters will increment, according to the rules in the table below, at the next instruction- or data fetch.

Table 1. Profiling counters
Profiling counter	Description
HIT	Incremented on a cache hit
MISS	Incremented on a cache miss (not counting write misses)

Registers

Instances


Instance	Domain	Base address	Description
ICACHE	APPLICATION	0xE0082000	Instruction cache

Configuration


Instance	Domain	Configuration
ICACHE	APPLICATION	Cache size: 8 KB. Sets: 128. Data unit: 64 bits. Line width = 4 data units. Data bus width : 0..63

Register overview


Register	Offset	Description
TASKS_INVALIDATECACHE	0x008	Invalidate the cache.
STATUS	0x400	Status of the cache activities.
ENABLE	0x404	Enable cache.
PROFILING.ENABLE	0x414	Enable the profiling counters.
PROFILING.CLEAR	0x418	Clear the profiling counters.
PROFILING.HIT	0x41C	The cache hit counter for cache region.
PROFILING.MISS	0x420	The cache miss counter for cache region.

TASKS_INVALIDATECACHE

Address offset: 0x008

Invalidate the cache.

The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_INVALIDATECACHE										Invalidate the cache. The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.
			Trigger	1								Trigger task

STATUS

Address offset: 0x400

Status of the cache activities.

Indicates status of the activities initiated using respective tasks.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	READY										Ready status.
			Ready	0								Activity is done and ready for the next activity.
			Busy	1								Activity is in progress.

ENABLE

Address offset: 0x404

Enable cache.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable cache
			Disabled	0								Disable cache
			Enabled	1								Enable cache

PROFILING.ENABLE

Address offset: 0x414

Enable the profiling counters.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable the profiling counters
			Disable	0								Disable profiling
			Enable	1								Enable profiling

PROFILING.CLEAR

Address offset: 0x418

Clear the profiling counters.

The profiling counters can be cleared at any time. When cleared, all profiling counters will be set to zero, and will increment at the next instruction- or data fetch.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	CLEAR										Clearing the profiling counters
			Clear	1								Clear the profiling counters

PROFILING.HIT

Address offset: 0x41C

The cache hit counter for cache region.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HITS										Number of cache hits

PROFILING.MISS

Address offset: 0x420

The cache miss counter for cache region.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MISSES										Number of cache misses