SWI — Software interrupts

A set of interrupts have been reserved for use as software interrupts.

These interrupts can be enabled and triggered by software by using the Arm® Cortex®-M33 NVIC registers, as described in the Arm Cortex-M33 Processor Technical Reference Manual.

Registers

Instances

InstanceDomainBase addressDescription
SWI00APPLICATION0x4001C000

Software interrupt SWI00

SWI01APPLICATION0x4001D000

Software interrupt SWI01

SWI02APPLICATION0x4001E000

Software interrupt SWI02

SWI03APPLICATION0x4001F000

Software interrupt SWI03