DPPI — Distributed programmable peripheral interconnect

The distributed programmable peripheral interconnect (DPPI) enables peripherals to interact autonomously with each other through tasks and events, without CPU intervention. DPPI allows precise synchronization between peripherals when real-time application constraints exist, and eliminates the need for CPU involvement to implement behavior which can be predefined using the DPPI.

Note: For more information on tasks, events, publish, subscribe, interrupts, and other concepts, see Peripheral interface.

The main features of DPPI are the following:

The DPPI consists of several PPIBus modules. These modules are connected to a fixed number of DPPI channels and a DPPI controller (DPPIC).

Figure 1. DPPI overview
DPPI overview, block diagram

Channel publish and subscribe

The DPPI system directs peripheral events to a channel (publishing) and converts events from a channel into peripheral tasks (subscribing).

All peripherals include the following:

  • One publish register per event
  • One subscribe register per task

The publish and subscribe registers have two fields. A channel index field (CHIDX) determines which channel an event is published to, or which channel a task is subscribed to. In addition there is an ENABLE field that must be set to 1 to activate the operation.

Writing non-existing channel index (CHIDX) numbers into a peripheral's publish or subscribe registers will yield unexpected results.

One event can trigger multiple tasks by subscribing different tasks to the same channel. Similarly, one task can be triggered by multiple events by publishing different events to the same channel. For advanced use cases, multiple events and multiple tasks can connect to the same channel forming a many-to-many connection. If multiple events are published on the same channel at the same time, the events are merged and only one event is routed through the DPPI.

The following figure shows how peripheral events are routed onto different channels based on publish registers.

Figure 2. DPPI events flow
DPPI events flow

The following figure illustrates how peripheral tasks are triggered from different channels based on subscribe registers.

Figure 3. DPPI tasks flow
DPPI tasks flow

DPPI controller (DPPIC)

Enabling and disabling of DPPI channels is handled through DPPIC.

There are two ways of enabling or disabling a DPPI channel using DPPIC:

  • Enable or disable channels individually using registers CHEN, CHENSET, and CHENCLR.
  • Enable or disable channels in channel groups using the groups' tasks ENABLE and DISABLE. Channel groups should be defined via the CHG registers before these tasks are triggered.
Note: ENABLE tasks are prioritized over DISABLE tasks, i.e. in case of a simultaneously occurring TASKS_CHG[m].EN and TASKS_CHG[n].DIS (m and n can be equal or different), the CHG[m].EN task will be prioritized if the same channel subscribed to both groups.

DPPIC tasks (for example CHG[0].EN) can be triggered through DPPI like any other task, which means they can be linked to a DPPI channel through the subscribe registers.

In order to write to CHG[n], the corresponding CHG[n].EN and CHG[n].DIS subscribe registers must be disabled. Writes to CHG[n] are ignored if any of the two subscribe registers are enabled.

Connection examples

Several connection options are available with DPPI. Examples are given for how to create one-to-one and many-to-many connections.

One-to-one connection

This example shows how to create a one-to-one connection between the TIMER compare register and the SAADC start task.

The channel configuration is set up first. TIMER will publish its COMPARE0 event on channel 0, and SAADC will subscribe its START task to events on the same channel. When this is finished, the channel is enabled through the DPPIC.


NRF_TIMER20->PUBLISH_COMPARE[0] = (0 << TIMER_PUBLISH_COMPARE_CHIDX_Pos) | TIMER_PUBLISH_COMPARE_EN_Msk;
NRF_SAADC->SUBSCRIBE_START = (0 << SAADC_SUBSCRIBE_START_CHIDX_Pos) | SAADC_SUBSCRIBE_START_EN_Msk;
NRF_DPPIC20->CHENSET = DPPIC_CHENSET_CH0_Msk;
            

Many-to-many connection

The following example shows how to create a many-to-many connection, showcasing the DPPIC's channel group functionality.

A channel group that includes only channel 0 is set up first. Then the GPIOTE and TIMER configure their IN0 and COMPARE0 events respectively to be published on channel 0, while the SAADC configures its START task to subscribe to events on channel 0. Through DPPIC, the CHG0 DISABLE task is configured to subscribe to events on channel 0. After an event is received on channel 0 it will be disabled. Finally, channel 0 is enabled using the DPPIC task to enable a channel group.

NRF_DPPIC20->CHG[0] = (DPPIC_CHG_CH0_Included << DPPIC_CHG_CH0_Pos);
NRF_GPIOTE20->PUBLISH_IN[0] = (0 << GPIOTE_PUBLISH_IN_CHIDX_Pos) | GPIOTE_PUBLISH_IN_EN_Msk;
NRF_TIMER20->PUBLISH_COMPARE[0] = (0 << TIMER_PUBLISH_COMPARE_CHIDX_Pos) | TIMER_PUBLISH_COMPARE_EN_Msk;
NRF_SAADC->SUBSCRIBE_START = (0 << SAADC_SUBSCRIBE_START_CHIDX_Pos) | SAADC_SUBSCRIBE_START_EN_Msk;
NRF_DPPIC20->SUBSCRIBE_CHG[0].DIS = DPPIC_CHENSET_CH0_Msk | DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk;
NRF_DPPIC20->TASK_CHG[0].EN = 1;
                

Registers

Instances

InstanceDomainBase addressDescription
DPPIC00GLOBAL0x40042000

DPPI controller DPPIC00

DPPIC10GLOBAL0x40082000

DPPI controller DPPIC10

DPPIC20GLOBAL0x400C2000

DPPI controller DPPIC20

DPPIC30GLOBAL0x40102000

DPPI controller DPPIC30

Configuration

InstanceDomainConfiguration
DPPIC00GLOBAL

16 DPPI channels

2 DPPI groups

DPPIC10GLOBAL

24 DPPI channels

6 DPPI groups

DPPIC20GLOBAL

16 DPPI channels

6 DPPI groups

DPPIC30GLOBAL

4 DPPI channels

2 DPPI groups

Register overview

RegisterOffsetDescription
TASKS_CHG[n].EN0x000

Enable channel group n

TASKS_CHG[n].DIS0x004

Disable channel group n

SUBSCRIBE_CHG[n].EN0x080

Subscribe configuration for task CHG[n].EN

SUBSCRIBE_CHG[n].DIS0x084

Subscribe configuration for task CHG[n].DIS

CHEN0x500

Channel enable register

CHENSET0x504

Channel enable set register

CHENCLR0x508

Channel enable clear register

CHG[n]0x800

Channel group n

Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled

TASKS_CHG[n]

Channel group tasks

TASKS_CHG[n].EN

Address offset: 0x000 + (n × 0x8)

Enable channel group n

Bit number313029282726252423222120191817161514131211109876543210
IDA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A

W

EN

Enable channel group n

Trigger

1

Trigger task

TASKS_CHG[n].DIS

Address offset: 0x004 + (n × 0x8)

Disable channel group n

Bit number313029282726252423222120191817161514131211109876543210
IDA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A

W

DIS

Disable channel group n

Trigger

1

Trigger task

SUBSCRIBE_CHG[n]

Subscribe configuration for tasks

SUBSCRIBE_CHG[n].EN

Address offset: 0x080 + (n × 0x8)

Subscribe configuration for task CHG[n].EN

Bit number313029282726252423222120191817161514131211109876543210
IDBAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A

RW

CHIDX

[0..255]

DPPI channel that task CHG[n].EN will subscribe to

B

RW

EN

Disabled

0

Disable subscription

Enabled

1

Enable subscription

SUBSCRIBE_CHG[n].DIS

Address offset: 0x084 + (n × 0x8)

Subscribe configuration for task CHG[n].DIS

Bit number313029282726252423222120191817161514131211109876543210
IDBAAAAAAAA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A

RW

CHIDX

[0..255]

DPPI channel that task CHG[n].DIS will subscribe to

B

RW

EN

Disabled

0

Disable subscription

Enabled

1

Enable subscription

CHEN

Address offset: 0x500

Channel enable register

Bit number313029282726252423222120191817161514131211109876543210
IDXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A-X

RW

CH[i] (i=0..23)

Enable or disable channel i

Disabled

0

Disable channel

Enabled

1

Enable channel

CHENSET

Address offset: 0x504

Channel enable set register

Note: Read: Reads value of CH[i] field in CHEN register
Bit number313029282726252423222120191817161514131211109876543210
IDXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A-X

RW
W1S

CH[i] (i=0..23)

Channel i enable set register. Writing 0 has no effect.

Disabled

0

Read: Channel disabled

Enabled

1

Read: Channel enabled

Set

1

Write: Enable channel

CHENCLR

Address offset: 0x508

Channel enable clear register

Note: Read: Reads value of CH[i] field in CHEN register
Bit number313029282726252423222120191817161514131211109876543210
IDXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A-X

RW
W1C

CH[i] (i=0..23)

Channel i enable clear register. Writing 0 has no effect.

Disabled

0

Read: Channel disabled

Enabled

1

Read: Channel enabled

Clear

1

Write: Disable channel

CHG[n]

Address offset: 0x800 + (n × 0x4)

Channel group n

Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled

Bit number313029282726252423222120191817161514131211109876543210
IDXWVUTSRQPONMLKJIHGFEDCBA
Reset 0x0000000000000000000000000000000000000000
IDR/WFieldValue IDValueDescription
A-X

RW

CH[i] (i=0..23)

Include or exclude channel i

Excluded

0

Exclude

Included

1

Include