CRACEN TRNG — True Random Number Generator

The NIST-800-90B non-deterministic, true random number generator, can be used by cryptographic modules as an entropy source.

The entropy source is a set of distinct oscillator rings, where each ring is composed of an odd number of inverters and oscillates at a much higher frequency than the digital sampling frequency. The analog signal from all rings is converted into a digital signal by sampling it at a regular clock frequency.

It is possible to observe the samples from this noise source by bypassing the conditioning function (by setting the bit CONTROL.CONDBYPASS to 1).

There are 4 shares (sets) of 8 distinct ring oscillators. The output bitstream from each set has its own set of tests as described in Continuous Testing. These bitstreams are merged by a blender to produce a single stream of entropy.

The most efficient way to generate random data with minimal latency is to concatenate the ring oscillator output streams (the hardware default). However, these outputs can be blended to increase entropy. The blender can be configured to use different methods for entropy enhancement via the BLENDINGMETHOD field. XORLEVEL1 reduces 4×8 bits to 4 bits, while XORLEVEL2 further reduces the 4 bits to 1. Another blending option is the Von-Neumann debiasing algorithm (VONNEUMANN), which assumes the input bits are independent and identically distributed (IID), producing a likely uniform output. When the Von-Neumann debiasing method is selected, the XORLEVEL1 and XORLEVEL2 compression methods are applied first, then 00 and 11 bit pairs are discarded while 10 and 01 pairs are retained, with only the first bit of each retained pair being output.

When the output node of a high frequency ring oscillator (RO) is sampled at the rate of a low-frequency clock, then the sampled bit is random. The device ensures that T_osc >> T_RO, where T_osc is the duration during which the ring oscillator is free-running.

Two oscillation modes are supported: warm mode and cold mode.

In warm mode, the ring oscillators are free-running as long as the FIFO is being filled. Warm mode is selected by writing register COOLDOWNPERIOD = 0. A sample is taken every D_OSC clock cycles, where D_OSC is configured using the SAMPLINGPERIOD register. Note that the oscillation time T_OSC = D_OSC * T_CLK.

In cold mode, the ring oscillators are disabled for D_RST clock cycles after every sample. D_RST is configured through the COOLDOWNPERIOD register.

Note that in reality D_OSC is typically larger than what is suggested by the above figures, ensuring that T_OSC >> T_RST.

Warm mode could theoretically exhibit temporal correlations, unlike cold mode, which is rendered memoryless by resetting to a predefined state before each random data generation. To mitigate this in warm mode, an additional margin can be applied to T_OSC, by using the SAMPLINGPERIOD register. Health tests will activate if issues arise.

Cold mode may be more susceptible to side-channel attacks, as the cessation of oscillation offers a synchronization point, potentially allowing an attacker to more readily determine when samples are generated. Warm mode is not entirely immune to such vulnerabilities either, because the AES can produce a power signature that also serves as a synchronization point.

The warm mode will have a better throughput.

The choice between the two options depends on the application requirements. Both approaches are valid and pass the relevant test suites .

The samples from entropy source are monitored permanently by repetition and proportion tests running in parallel. Tests are run on the raw samples, i.e. not influenced by the CONTROL.BLENDINGMETHOD setting. Optionally, correlation and auto-correlation tests can be used as well.

The repetition count test as described in section 4.4.1 of NIST Special Publication 800-90 is implemented. The acceptable false-positive rate defaults to α = 2^-20.

For a min-entropy of H=8.0, the default repetition cut-off value (REPEATTHRESHOLD) is 4. Test can be disabled via DISREPETTESTS bit in the CONTROL register. Failures in the repetition test for each share are reported in the REPTESTFAILPERSHARE bits in the STATUS register.

The proportion count test as described in section 4.4.2 of NIST Special Publication 800-90 has been implemented with a window size of W = 512 non-binary samples. The acceptable false-positive rate has been fixed to α = 2^-20. The entropy source delivers 1-bit sample and after chosen blending method non-binary samples are created. For a min-entropy of H=8.0, default proportion cut-off value is C = 1+CRITBINOM(W, 2^-H,1-α) = 13. Cut-off value is programmed in PROPTESTCUTOFF register. This test can be disabled via CONTROL.DISPROPTESTS. Failing per share proportion test is reported via STATUS.PROPTESTFAILPERSHARE.

Compliant with NIST-800-90B, the Repetition Count Test and the Adaptive Proportion Test are required to pass before any data is read from the FIFO.

When two ring oscillators are coupled through injection locking, their bitstreams become correlated. Correlation count test can detect this occurrence. It uses time-division multiplexing and even single pair of ring oscillators case is supported. Window size of W = 128 samples is used with cut-off values defined in CORRTESTCUTOFF registers. Specific delay checks (or all checks) can be disabled via CONTROL.DISCORRTESTS.

When a ring oscillator is continuously sampled without accumulating enough jitter, the produced bitstream shows periodic behavior. Autocorrelation count test is able to detect this behavior. It uses time-division multiplexing and even single ring oscillator case is supported. Window size of W = 128 samples is used with cut-off values defined as in AUTOCORRTESTCUTOFF registers. Specific delay checks (or all checks) can be disabled via CONTROL.DISAUTOCORRTESTS.

The CBC-MAC mode (as described in section 3.1.5.1.1 and Appendix F in NIST Special Publication 800-90) of AES128 has been used as FIPS-approved keyed conditioning function. The conditioning function takes CONTROL.NB128BITBLOCKS x 128 bits from the entropy source as input and generates 128 bits as output. Assuming a min-entropy of 50% and NB128BITBLOCKS = 4, the input entropy is hin=512 x 50%=256 bits. According to section 3.1.5.1.2 in NIST Special Publication 800-90, the output of the conditioning function can be considered to have 128 bits of full entropy. The conditioning function can be tested by sending known data (using TESTDATA with CONTROL.TESTEN=1).

The output entropy is split into 32-bit words and stored in the output FIFO. The FIFO size in 32-bit words can be read from the FIFODEPTH register. The FIFO operates as a single word stream - the first available word is returned regardless of which FIFO entry is accessed. When a word is read from the FIFO, the FIFOLEVEL register automatically decreases to reflect the number of remaining 32-bit random numbers. The FIFOTHRESHOLD register determines when the RNG state machine starts refilling the FIFO.

Depending on the configuration of the conditioning function, either raw noise samples or conditioned samples are written to the FIFO when the ENABLE bit is set. For details on the state machine that manages the filling of the FIFO, see Control FSM state diagram . If the CONTROL.FIFOWRITESTARTUP bit is set, the statemachine will start filling the FIFO immediately after the FIFO is enabled, ignoring startup failures. If the CONTROL.IGNOREHEALTHTESTSFAILFORFSM bit is set the state machine ignores all the health test failures and allows data to be written to the FIFO even if health tests fail. It is not recommended to set either of these bits, as it may lead to the FIFO being filled with data of poor quality.

The RNG is controlled by an finite state machine (FSM) which handles all the low-level interactions between the different hardware components described in Random number generator block diagram . During normal operation the FSM ensures that the entropy source is controlled in a NIST-800-90B compatible way, as shown in the following figure.

The state diagram does not show that asserting the hard or soft resets and/or de-asserting the enable bit cause the state to be reset to "Reset".

1. Apply software reset (RNGCONTROL.CONTROL.SOFTRST = 1)
2. Write the control register
   • CONTROL.NB128BITBLOCKS=4
   • CONTROL.TESTEN=1
   • CONTROL.FIFOWRITESTARTUP=1
   • CONTROL.ENABLE=1
3. Write the KEY register
4. Write the data to the TESTDATA register (after each write, wait until the TESTDATABUSY flag becomes low)
5. Read the result from the FIFO

The table below shows an example of data (taken from section F.2.1 in NIST Special Publication 800-38A)

1. Apply software reset
2. Write the CONTROL register ensuring that none of the health tests are bypassed and set the ENABLE bit.
3. Wait until the STATE is not Reset, Startup or Error. When this is the case, all start-up tests have passed and the entropy source is working correctly.
4. If the state is Error, select different values for SAMPLINGPERIOD and WARMUPPERIOD and go back to 1.

1. Check the FIFOLEVEL register to monitor the amount of generated random numbers or wait for the FULLINT IRQ.
2. When FIFOLEVEL has reached the expected value or when an IRQ has been received, read the random numbers from the FIFO.
3. Use 4 x 32-bit random values to program a random key in the KEY register.
4. Apply software reset to flush the FIFO. By toggling the SOFTRST bit in the CONTROL register.

1. Check the FIFOLEVEL register to monitor the amount of generated random numbers or wait for the FIFOFULL IRQ.
2. When FIFOLEVEL has reached the expected value or when an IRQ has been received, read the random numbers from the FIFO.

1. Disable the RNG (set the ENABLE bit of the CONTROL register to 0)
2. Configure the CONTROL register
3. Do a soft reset to have a clean starting point (set bit SOFTRST of the CONTROL register to 1)
4. Enable the RNG back (set the ENABLE bit of the CONTROL register to 1 while clearing the SOFTRST bit)

All cryptographic data are handled following the big-endian format (AES standard). That means that the first byte (lowest address) of the data is the Most Significant Byte (MSB).

The APB bus uses little endian format. That means that the Least Significant Byte (LSB) is stored at the lowest address.

For example, a 128-bit block D[A] = 0x00112233445566778899AABBCCDDEEFF stored at address A (multiple of 4) appears on APB bus as the following 32-bit words:

• D[A+0] = 0x33221100
• D[A+4] = 0x77665544
• D[A+8] = 0xBBAA9988
• D[A+12] = 0xFFDDEEC

When conditioning is enabled, the number of cycles required for the RNG to generate the first N words of data can be estimated with the following formula:

Nbcycles ≈ C + 1024 * (SAMPLINGPERIOD + COOLDOWNPERIOD) + 128 * NB128BITBLOCKS * max(1/8, (SAMPLINGPERIOD + COOLDOWNPERIOD + 1) * BLENDING_RATIO / 128) * max(0, N - 4) + WARMUPPERIOD

where C is the number of cycles required to initialize the RNG state machine.

BLENDING_RATIO is the ratio of bit reduction due to the chosen BLENDINGMETHOD (1 for CONCATENATION, 8 for XORLEVEL1, 32 for XORLEVEL2, and 128 for VONNEUMANN).

To enable the RNG interrupt, enable the RNG field in the CRACEN.INTEN register and set the necessary INTEN bits in the CRACENCORE.RNGCONTROL.CONTROL register.

The RNG has two interrupt causes:

• FULLINT: set when the FIFO becomes full. It can be cleared when FIFO is no longer full by writing to the FIFOLEVEL register or activating soft-reset.
• ANYHEALTHTESTFAIL: set when an error is detected in any of the health tests. It is cleared when writing a zero to the corresponding bit in the status register or when the soft-reset is activated.

For each interrupt, there is a status bit in the STATUS register and an enable bit in the CONTROL register. The STATUS register state does not depend on the interrupt enable bits in the control register. The interrupt enable bits are only used to control the generation of the event CRACEN.EVENTS_RNG and the signal to the interrupt handler.