ECB — AES electronic codebook mode encryption
The AES electronic codebook mode encryption (ECB) can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. The ECB encryption block supports 128 bit AES encryption (encryption only, not decryption).
The main features of ECB are:
- 128-bit AES encryption
- Supports standard AES ECB block encryption
- Memory-to-memory operations using Scatter/Gather DMA
The inputs and outputs of the ECB are illustrated below.
AES ECB uses EasyDMA with scatter-gather to access to memory for in-place operations on cleartext and ciphertext during encryption. ECB uses the same AES core as the CCM and AAR blocks and is an asynchronous operation which may not complete if the AES core is busy.
AES ECB performs a 128 bit AES block encrypt. At the START task, cleartext is loaded into the ECB from memory described by the scatter/gather job list pointed to by INPTR and the ciphertext is written into memory described by the job list pointed to by OUTPTR. When the last cleartext byte has been encrypted and written to OUTPTR, the END event is triggered.
The following figure illustrates how the input and output job lists can be configured. For more details of the joblists, see EasyDMA.
The AES key is set by writing the KEY.VALUE key registers. The same key can be used to encrypt multiple blocks by triggering the START task multiple times.
AES ECB can be stopped by triggering the STOP task.
- If less than 16 bytes is supplied as input, then a PrematureInptrEnd error is triggered. The EVENTS_ERROR will also be set.
- If more than 16 bytes is supplied as input, then only the first 16 bytes are used.
- For an output job, only the number of bytes specified in the job list are copied to memory.
- Key: 4C68384139F574D836BCF34E9DFB01BF
- Plaintext: 0213243546576879acbdcedfe0f10213
- Expected Encrypted Output: 99ad1b5226a37e3e058e3b8e27c2c666
- KEY.VALUE[0] = 0x9DFB01BF
- KEY.VALUE[1] = 0x36BCF34E
- KEY.VALUE[2] = 0x39F574D8
- KEY.VALUE[3] = 0x4C683841
{0x02, 0x13, 0x24, 0x35, 0x46, 0x57, 0x68, 0x79, 0xAC, 0xBD, 0xCE, 0xDF, 0xE0, 0xF1, 0x02, 0x13}
Once the encryption is complete, the output buffer referenced by the output job will be filled with the following 16-byte array:
{0x99, 0xAD, 0x1B, 0x52, 0x26, 0xA3, 0x7E, 0x3E, 0x05, 0x8E, 0x3B, 0x8E, 0x27, 0xC2, 0xC6, 0x66}
Shared resources
The ECB shares the same AES module as the AAR and CCM peripherals. The ECB will always have lowest priority. If there is a sharing conflict during encryption, the ECB operation will be aborted and an ERROR event will be generated.
EasyDMA
This peripheral implements EasyDMA with scatter-gather functionality for reading from and writing to memory without CPU involvement.
The scatter-gather functionality allows EasyDMA to collect data from multiple memory regions, instead of one contigous block. The memory regions are described by a job list. The job list consists of one or more job entries that consist of a 32-bit address field, 8-bit attribute field, and 24-bit length field. A job list ends with a zero filled job entry. The attribute field must be set to 11.
If INPTR or OUTPTR pointers or the entries in the job lists are not pointing to memory connected to the DMA bus, an EasyDMA transfer may result in a HardFault or memory corruption. See Memory for more information about the different memory regions and DMA connectivity.
The EasyDMA will have finished accessing the RAM when the END or ERROR events are generated.
For instances supporting DMA error detection, the ERRORSTATUS register will report if a bus error has occurred during DMA access. To see if DMA error detection is supported, see the the instance's configuration in Instantiation.
Example
- FIRSTDATA, an array of length 3
- SECONDDATA, an array of length 2
- THIRDDATA, an array of length 11
Registers
Instances
| Instance | Domain | Base address | Description |
|---|---|---|---|
| ECB00 | GLOBAL | 0x4004B000 | AES ECB mode encryption 00 |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
| ECB00 | GLOBAL |
Register overview
| Register | Offset | Description |
|---|---|---|
| TASKS_START | 0x000 | Start ECB block encrypt |
| TASKS_STOP | 0x004 | Abort a possible executing ECB operation |
| SUBSCRIBE_START | 0x080 | Subscribe configuration for task START |
| SUBSCRIBE_STOP | 0x084 | Subscribe configuration for task STOP |
| EVENTS_END | 0x100 | ECB block encrypt complete |
| EVENTS_ERROR | 0x104 | ECB block encrypt aborted because of a STOP task or due to an error |
| PUBLISH_END | 0x180 | Publish configuration for event END |
| PUBLISH_ERROR | 0x184 | Publish configuration for event ERROR |
| INTENSET | 0x304 | Enable interrupt |
| INTENCLR | 0x308 | Disable interrupt |
| ERRORSTATUS | 0x400 | Error status |
| KEY.VALUE[n] | 0x510 | 128-bit AES key |
| IN.PTR | 0x530 | Input pointer |
| OUT.PTR | 0x538 | Output pointer Points to a job list containing encrypted ECB data structure |
| CSAA.REFLECTOR | 0x53C | Selected Channel Sounding Access Address used in the CS SYNC from Reflector to Initiator |
| CSAA.INITIATOR | 0x540 | Selected Channel Sounding Access Address used in the CS SYNC from Initiator to Reflector |
| CSAA.MODE | 0x544 | Operation modes |
TASKS_START
Address offset: 0x000
Start ECB block encrypt
If a crypto operation is already running in the AES core, the START task will not start a new encryption and an ERROR event will be triggered
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | ||||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | W | TASKS_START | Start ECB block encrypt If a crypto operation is already running in the AES core, the START task will not start a new encryption and an ERROR event will be triggered | ||||||||||||||||||||||||||||||||
Trigger | 1 | Trigger task | |||||||||||||||||||||||||||||||||
TASKS_STOP
Address offset: 0x004
Abort a possible executing ECB operation
If a running ECB operation is aborted by STOP, the ERROR event is triggered.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | ||||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | W | TASKS_STOP | Abort a possible executing ECB operation If a running ECB operation is aborted by STOP, the ERROR event is triggered. | ||||||||||||||||||||||||||||||||
Trigger | 1 | Trigger task | |||||||||||||||||||||||||||||||||
SUBSCRIBE_START
Address offset: 0x080
Subscribe configuration for task START
If a crypto operation is already running in the AES core, the START task will not start a new encryption and an ERROR event will be triggered
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | CHIDX | [0..255] | DPPI channel that task START will subscribe to | |||||||||||||||||||||||||||||||
| B | RW | EN | |||||||||||||||||||||||||||||||||
Disabled | 0 | Disable subscription | |||||||||||||||||||||||||||||||||
Enabled | 1 | Enable subscription | |||||||||||||||||||||||||||||||||
SUBSCRIBE_STOP
Address offset: 0x084
Subscribe configuration for task STOP
If a running ECB operation is aborted by STOP, the ERROR event is triggered.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | CHIDX | [0..255] | DPPI channel that task STOP will subscribe to | |||||||||||||||||||||||||||||||
| B | RW | EN | |||||||||||||||||||||||||||||||||
Disabled | 0 | Disable subscription | |||||||||||||||||||||||||||||||||
Enabled | 1 | Enable subscription | |||||||||||||||||||||||||||||||||
EVENTS_END
Address offset: 0x100
ECB block encrypt complete
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | ||||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | EVENTS_END | ECB block encrypt complete | ||||||||||||||||||||||||||||||||
NotGenerated | 0 | Event not generated | |||||||||||||||||||||||||||||||||
Generated | 1 | Event generated | |||||||||||||||||||||||||||||||||
EVENTS_ERROR
Address offset: 0x104
ECB block encrypt aborted because of a STOP task or due to an error
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | ||||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | EVENTS_ERROR | ECB block encrypt aborted because of a STOP task or due to an error | ||||||||||||||||||||||||||||||||
NotGenerated | 0 | Event not generated | |||||||||||||||||||||||||||||||||
Generated | 1 | Event generated | |||||||||||||||||||||||||||||||||
PUBLISH_END
Address offset: 0x180
Publish configuration for event END
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | CHIDX | [0..255] | DPPI channel that event END will publish to | |||||||||||||||||||||||||||||||
| B | RW | EN | |||||||||||||||||||||||||||||||||
Disabled | 0 | Disable publishing | |||||||||||||||||||||||||||||||||
Enabled | 1 | Enable publishing | |||||||||||||||||||||||||||||||||
PUBLISH_ERROR
Address offset: 0x184
Publish configuration for event ERROR
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | CHIDX | [0..255] | DPPI channel that event ERROR will publish to | |||||||||||||||||||||||||||||||
| B | RW | EN | |||||||||||||||||||||||||||||||||
Disabled | 0 | Disable publishing | |||||||||||||||||||||||||||||||||
Enabled | 1 | Enable publishing | |||||||||||||||||||||||||||||||||
INTENSET
Address offset: 0x304
Enable interrupt
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | B | A | |||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | END | Write '1' to enable interrupt for event END | ||||||||||||||||||||||||||||||||
Set | 1 | Enable | |||||||||||||||||||||||||||||||||
Disabled | 0 | Read: Disabled | |||||||||||||||||||||||||||||||||
Enabled | 1 | Read: Enabled | |||||||||||||||||||||||||||||||||
| B | RW | ERROR | Write '1' to enable interrupt for event ERROR | ||||||||||||||||||||||||||||||||
Set | 1 | Enable | |||||||||||||||||||||||||||||||||
Disabled | 0 | Read: Disabled | |||||||||||||||||||||||||||||||||
Enabled | 1 | Read: Enabled | |||||||||||||||||||||||||||||||||
INTENCLR
Address offset: 0x308
Disable interrupt
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | B | A | |||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | END | Write '1' to disable interrupt for event END | ||||||||||||||||||||||||||||||||
Clear | 1 | Disable | |||||||||||||||||||||||||||||||||
Disabled | 0 | Read: Disabled | |||||||||||||||||||||||||||||||||
Enabled | 1 | Read: Enabled | |||||||||||||||||||||||||||||||||
| B | RW | ERROR | Write '1' to disable interrupt for event ERROR | ||||||||||||||||||||||||||||||||
Clear | 1 | Disable | |||||||||||||||||||||||||||||||||
Disabled | 0 | Read: Disabled | |||||||||||||||||||||||||||||||||
Enabled | 1 | Read: Enabled | |||||||||||||||||||||||||||||||||
ERRORSTATUS
Address offset: 0x400
Error status
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | A | A | ||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | R | ERRORSTATUS | Error status when the ERROR event is generated | ||||||||||||||||||||||||||||||||
NoError | 0 | No errors have occurred | |||||||||||||||||||||||||||||||||
PrematureInptrEnd | 1 | End of INPTR job list before data structure was read. | |||||||||||||||||||||||||||||||||
PrematureOutptrEnd | 2 | End of OUTPTR job list before data structure was read. | |||||||||||||||||||||||||||||||||
EncryptionTooSlow | 3 | Encryption aborted due to higher priority peripheral requesting or using the AES module. This enumerator is deprecated. | |||||||||||||||||||||||||||||||||
Aborted | 3 | Encryption aborted due to higher priority peripheral requesting or using the AES module. | |||||||||||||||||||||||||||||||||
DmaError | 4 | Bus error during DMA access. | |||||||||||||||||||||||||||||||||
KEY.VALUE[n]
Address offset: 0x510 + (n × 0x4)
128-bit AES key
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | W | VALUE | AES 128-bit key value, bits (32*(n+1))-1 : (32*n) | ||||||||||||||||||||||||||||||||
IN
IN EasyDMA channel
IN.PTR
Address offset: 0x530
Input pointer
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | PTR | Points to a job list containing unencrypted ECB data structure | ||||||||||||||||||||||||||||||||
OUT
OUT EasyDMA channel
OUT.PTR
Address offset: 0x538
Output pointer
Points to a job list containing encrypted ECB data structure
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | PTR | Output pointer | ||||||||||||||||||||||||||||||||
CSAA
Channel sounding access address scoring algorithm
CSAA.REFLECTOR
Address offset: 0x53C
Selected Channel Sounding Access Address used in the CS SYNC from Reflector to Initiator
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | R | PN | |||||||||||||||||||||||||||||||||
CSAA.INITIATOR
Address offset: 0x540
Selected Channel Sounding Access Address used in the CS SYNC from Initiator to Reflector
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | R | PN | |||||||||||||||||||||||||||||||||
CSAA.MODE
Address offset: 0x544
Operation modes
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | ||||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A | RW | BITREVERSE | Reverse the endianness on bit level for the ECB output, INITIATOR, and REFLECTOR registers Enable bit reversal on each byte. | ||||||||||||||||||||||||||||||||
Default | 0 | Default endianness | |||||||||||||||||||||||||||||||||
Reversed | 1 | Reversed endianness | |||||||||||||||||||||||||||||||||