Pin assignments

The pin assignment figures and tables describe the pinouts for the product variants of the device.

The nRF54LS05A/nRF54LS05B device provides flexibility regarding GPIO pin routing and configuration. Some pins have limitations or recommendations on how the pin should be configured or what it should be used for.

As a general rule, peripherals must use GPIO pins in their own domain, and can be used for all peripheral functions when selected in the peripheral's PSEL register. Note the dedicated clock pin requirements listed in the following chapter. In addition, there are some dedicated pin functions that allows pin connections between different power domains.

The block diagram shows which peripheral and port belong together, see Block diagram.

The different GPIO ports have different properties. For details, see GPIO — General purpose input/output.

Dedicated pins

The device has some pins dedicated for specific purposes. GPIO pin routing and configuration is flexible. Some pins have limitations or recommendations for configuration and use.

Table 1. Dedicated pin functions
Function or peripheral	Description
GRTC	Has dedicated pins for clock and PWM output.
SWD	The debug interface has dedicated pins. With some restrictons, these pins can also be used as GPIO pins as described in the following section.
Weak pull-ups	A set of GPIO pins have additional pull-up options, all enabled by a single registers. For more details, see GPIO — General purpose input/output.

SWD pins

The serial wire debug (SWD) pins can be used as GPIO pins when debugging is not active.

These pins default to SWD functionality at reset, and can be configured as GPIO pins using the PROTECT.GPIOSWD signal protector interface of TAMPC. Once configured as GPIO pins, the SWD functionality and all SWD-related debug operations are disabled until the next reset. The debugger will not be able to wake the device from sleep or from System OFF mode through the SWD interface, but must instead use the pin reset (nRESET) to reset the device.

The pins shall only be used as outputs, connected to high impedant loads. This ensures that the pins do not load the debug interface when debugging is enabled. Failure to do so can cause the device SWD operations to malfunction.

The debugger can prevent the device from using the SWD pins as GPIOs by holding SWDCLK high when nRESET is de-asserted. This forces the device to keep the SWD functionality enabled.

Clock pins

The device has dedicated clock pins.

Some peripherals have clock signals. Dedicated clock pins have been optimized to ensure correct timing relationship between clock and data signals for these peripherals. See the following table for which peripheral signals must use clock pins. The pin assignment table identifies clock pins.

Clock pins can also be used as regular I/O data pins.

The peripheral data signal must be configured to use pins close to the clock pin. This ensures that the internal paths from the peripheral to the pin have the same delay, so that the data and clock signals reach the pins at the same time.

For high-speed signals, the printed circuit board (PCB) layout must use short PCB traces of identical length. This makes sure any delays are kept to a minimum, with close to identical delay on the clock and data path.

The following table shows which peripheral signals must use clock pins.

Table 2. List of peripheral signals and clock pin requirement
Peripheral	Signal	Clock pin required
SPIM/SPIS	SDO
	SDI
	SCK	x
	CSN
	DCX
TWIM/TWIS	SCL	x
GRTC	CLKOUT32K	x (dedicated pin)
	PWM	x (dedicated pin)
	CLKOUTFAST	x (dedicated pin)

QFN48 (QFAA) package pin assignments

The QFN48 pin assignment figure and table describe the pinouts for this variant of the device.

Pins that can be used as clock signals are shown in as red in the figure. For more information about clock pins, see Clock pins.

Figure 1. QFN48 pin assignments, top view

Table 3. QFN48 pin assignments
Pin	Clock pin	Weak pull-up	Name	Function	Description	Dedicated function
1			P1.00 XL1	Digital I/O Analog input	General purpose I/O Connection for 32.768 kHz crystal
2			P1.01 XL2	Digital I/O Analog input	General purpose I/O Connection for 32.768 kHz crystal
3			P1.02	Digital I/O	General purpose I/O
4	Yes		P1.03	Digital I/O	General purpose I/O
5	Yes		P1.04 AIN0	Digital I/O Analog input	General purpose I/O Analog input
6			P1.05 AIN1	Digital I/O Analog input	General purpose I/O Analog input
7			P1.06 AIN2	Digital I/O Analog input	General purpose I/O Analog input
8			P1.07 AIN3	Digital I/O Analog input	General purpose I/O Analog input
9	Yes		P1.08 EXTREF	Digital I/O Digital I/O Analog input	General purpose I/O GRTC CLKOUTFAST External reference for SAADC	GRTC
10			P1.16	Digital I/O	General purpose I/O
11		Yes	P1.17	Digital I/O	General purpose I/O
12	Yes	Yes	P1.18	Digital I/O	General purpose I/O
13	Yes	Yes	P1.19	Digital I/O	General purpose I/O
14		Yes	P1.20	Digital I/O	General purpose I/O
15		Yes	P1.21	Digital I/O	General purpose I/O
16		Yes	P1.22	Digital I/O	General purpose I/O
17	Yes	Yes	P1.23	Digital I/O	General purpose I/O
18	Yes	Yes	P1.24	Digital I/O	General purpose I/O
19		Yes	P1.25	Digital I/O	General purpose I/O
20		Yes	P1.26	Digital I/O	General purpose I/O
21		Yes	P1.27	Digital I/O Weak pull-up	General purpose I/O Weak pull-up
22			P1.28	Digital I/O	General purpose I/O
23			P0.00	Digital I/O	General purpose I/O
24	Yes		P0.01	Digital I/O Digital I/O	General purpose I/O GRTC PWM	GRTC
25			SWDIO P1.29	Debug General purpose I/O	Serial wire data. Bidirectional with standard-drive and on-chip pull-down. GPIO with limitations.	See SWD pins.
26	Yes		SWDCLK P1.30	Debug General purpose I/O	Serial wire clock. Input with on-chip pull-up. GPIO with limitations.	See SWD pins.
27			P0.02	Digital I/O	General purpose I/O
28			P0.03	Digital I/O	General purpose I/O
29	Yes		P0.04	Digital I/O Digital I/O	General purpose I/O GRTC CLKOUT32K	GRTC
30			nRESET	Reset	Pin reset with on-chip pull-up
31			ANT	RF	Single ended radio antenna connection	See Reference circuitry for guidelines on how to ensure good RF performance.
32			VSS_PA	Power	Ground (radio supply)
33			DECRF	Power	0.9 V regulator supply decoupling	Must be connected to DECA. See Reference circuitry.
34			XC1	Analog input	Connection for 32 MHz crystal
35			XC2	Analog input	Connection for 32 MHz crystal
36			P1.31	Digital I/O	General purpose I/O
37			P1.09	Digital I/O	General purpose I/O
38			P1.10	Digital I/O	General purpose I/O
39	Yes		P1.11	Digital I/O	General purpose I/O
40	Yes		P1.12	Digital I/O	General purpose I/O
41			P1.13	Digital I/O	General purpose I/O
42			P1.14	Digital I/O	General purpose I/O
43			DECA	Power	0.9 V regulator supply decoupling	Must be connected to DECRF. See Reference circuitry.
44			VSS	Power	Ground
45			DECD	Power	0.9 V regulator supply decoupling
46			DCC	Power	DC/DC regulator output
47			VDD	Power	Power supply
48			P1.15	Digital I/O	General purpose I/O
49			VSS	Power	Ground pad (die pad)