CACHE — Instruction/data cache

The cache is two-way set associative with a least recently used (LRU) replacement policy. Both instruction and data accesses towards NVM memory are cached.

The cache has the following features:

4x64-bit cache line
Ability to enable/disable cache at run-time
Writes to cached memory are write-around and invalidate the cache line
Manual invalidation and erase support
Locking cache updates on cache misses
Performance hit/miss counter registers for profiling CACHE operations
Optional readable cache content for profiling
- Data, tag, valid, and most recently used (MRU) bits
- Can be disabled when not in use

The cache must be enabled by the ENABLE register.

Architecture

The following figure shows the cache architecture.

Cache Overview — Figure 1. Cache overview


Bit	Name	Description
V	Valid	Indicates if a cache entry is valid. All V fields are cleared when enabling the cache, invalidating the cache, or when changing CACHE mode.
MRU	Most Recently Used	Updated on each fetch from the cache to indicate which Way was used most recently. Used to drive the cache replacement policy.

Profiling

The cache provides a scoreboard that tracks the hits and misses within the cache.

The results are available through a set of registers that can be used to indicate how well the cache is performing.

Profiling is enabled using PROFILING.ENABLE. All profiling counters can be cleared at any time using PROFILING.CLEAR. After being cleared, the counters will increment, according to the rules in the table below, at the next instruction- or data fetch.

Table 1. Profiling counters
Profiling counter	Description
HIT	Incremented on a cache hit
MISS	Incremented on a cache miss (not counting write misses)
LMISS	Incremented when accessing different line than was accessed last time
READS	Incremented on a CPU read
WRITES	Incremented on a CPU write

Debug

The CPU is able to read internal cache memories and tags for debug purposes.

The content of data and tag RAM's are accessible through registers SET[n].WAY[o].INFO (n=0..127) (o=0..1) and SET[n].WAY[o].DU[p].DATA[q] (n=0..127) (o=0..1) (p=0..3) (q=0..1).

Debug access is prevented by using register DEBUGLOCK.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
ICACHE	APPLICATION	0xE0082000	HF	S	NA	No	Instruction cache

Configuration


Instance	Domain	Configuration
ICACHE	APPLICATION	Cache size: 8 KB. Sets: 128. Data unit: 64 bits. Line width = 4 data units. Supports line invalidation Supports cache erase Supports cache line maintain Supports extended profiling registers (LMISS / READS / WRITES) Supports debug lock Supports write lock Data bus width : 0..63

Register overview


Register	Offset	Description
TASKS_INVALIDATECACHE	0x008	Invalidate the cache.
TASKS_INVALIDATELINE	0x014	Invalidate the line.
TASKS_ERASE	0x020	Erase the cache.
STATUS	0x400	Status of the cache activities.
ENABLE	0x404	Enable cache.
LINEADDR	0x410	Memory address covered by the line to be maintained.
PROFILING.ENABLE	0x414	Enable the profiling counters.
PROFILING.CLEAR	0x418	Clear the profiling counters.
PROFILING.HIT	0x41C	The cache hit counter for cache region.
PROFILING.MISS	0x420	The cache miss counter for cache region.
PROFILING.LMISS	0x424	The cache line miss counter for cache region.
PROFILING.READS	0x428	Number of reads for cache region.
PROFILING.WRITES	0x42C	Number of writes for cache region.
DEBUGLOCK	0x430	Lock debug mode.
WRITELOCK	0x434	Lock cache updates.

TASKS_INVALIDATECACHE

Address offset: 0x008

Invalidate the cache.

The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_INVALIDATECACHE										Invalidate the cache. The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.
			Trigger	1								Trigger task

TASKS_INVALIDATELINE

Address offset: 0x014

Invalidate the line.

The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_INVALIDATELINE										Invalidate the line. The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.
			Trigger	1								Trigger task

TASKS_ERASE

Address offset: 0x020

Erase the cache.

The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_ERASE										Erase the cache. The STATUS is updated for this task. This task can be triggered only when the STATUS is ready.
			Trigger	1								Trigger task

STATUS

Address offset: 0x400

Status of the cache activities.

Indicates status of the activities initiated using respective tasks.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	READY										Ready status.
			Ready	0								Activity is done and ready for the next activity.
			Busy	1								Activity is in progress.

ENABLE

Address offset: 0x404

Enable cache.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable cache
			Disabled	0								Disable cache
			Enabled	1								Enable cache

LINEADDR

Address offset: 0x410

Memory address covered by the line to be maintained.

The line maintain activities are line invalidate, line clean and line flush.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ADDR										Address.

PROFILING.ENABLE

Address offset: 0x414

Enable the profiling counters.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable the profiling counters
			Disable	0								Disable profiling
			Enable	1								Enable profiling

PROFILING.CLEAR

Address offset: 0x418

Clear the profiling counters.

The profiling counters can be cleared at any time. When cleared, all profiling counters will be set to zero, and will increment at the next instruction- or data fetch.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	CLEAR										Clearing the profiling counters
			Clear	1								Clear the profiling counters

PROFILING.HIT

Address offset: 0x41C

The cache hit counter for cache region.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HITS										Number of cache hits

PROFILING.MISS

Address offset: 0x420

The cache miss counter for cache region.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MISSES										Number of cache misses

PROFILING.LMISS

Address offset: 0x424

The cache line miss counter for cache region.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	LMISSES										Number of cache line misses

PROFILING.READS

Address offset: 0x428

Number of reads for cache region.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	READS										Number of reads for cache region.

PROFILING.WRITES

Address offset: 0x42C

Number of writes for cache region.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	WRITES										Number of writes for cache region.

DEBUGLOCK

Address offset: 0x430

Lock debug mode.

Note: Debug mode can only be unlocked by a reset


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW1	DEBUGLOCK										Lock debug mode
			Unlocked	0								Debug mode unlocked
			Locked	1								Debug mode locked. Ignores any other value written.

WRITELOCK

Address offset: 0x434

Lock cache updates.

Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content already present in the cache. The write lock is applied to whole cache.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	WRITELOCK										Lock cache updates
			Unlocked	0								Cache updates unlocked
			Locked	1								Cache updates locked

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
ICACHEINFO	APPLICATION	0x02F10000	HF	S	NA	No	Instruction cache info

Configuration


Instance	Domain	Configuration
ICACHEINFO	APPLICATION	Number of sets : 0..127 Number of ways : 0..1 Number of data units : 0..3 Data width of a data unit : 0..1 words TAG width : 0..19

Register overview


Register	Offset	TZ	Description
SET[n].WAY[o].INFO	0x0		Cache information for SET[n], WAY[o].

SET[n].WAY[o].INFO

Address offset: 0x0 + (n × 0x8) + (o × 0x4)

Cache information for SET[n], WAY[o].


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				G	F			E	D	C	B					A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	TAG										Cache tag.
B-E	R	DUV[i] (i=0..3)										Data unit valid info. One info bit for each data unit in a line, LSB is the first data unit.
			Invalid	0								Invalid data unit
			Valid	1								Valid data unit
F	R	V										Line valid bit.
			Invalid	0								Invalid cache line
			Valid	1								Valid cache line
G	R	MRU										Most recently used way.
			Way0	0								Way0 was most recently used
			Way1	1								Way1 was most recently used

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
ICACHEDATA	APPLICATION	0x02F00000	HF	S	NA	No	Instruction cache data

Configuration


Instance	Domain	Configuration
ICACHEDATA	APPLICATION	Number of sets : 0..127 Number of ways : 0..1 Number of data units : 0..3 Data width of a data unit : 0..1 words

Register overview


Register	Offset	TZ	Description
SET[n].WAY[o].DU[p].DATA[q]	0x0		Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o].

SET[n].WAY[o].DU[p].DATA[q]

Address offset: 0x0 + (n × 0x40) + (o × 0x20) + (p × 0x8) + (q × 0x4)

Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o].


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	Data										Data