System OFF mode
System OFF is the deepest power-saving mode the system can enterafter Hibernate mode. In this mode, the system's core functionality is powered down and most ongoing tasks are stopped.
Register SYSTEMOFF sets the device into System OFF mode. The following wakeup sources will initiate a wakeup from System OFF:
- The DETECT signal generated by the GPIO peripheral
- The ANADETECT signal generated by the LPCOMP peripheral
- The SYSCOUNTER compare event generated by the GRTC peripheral
- A debug session is started
- A pin reset
When the device wakes up from System OFF, a system reset is performed. For more details, see Reset behavior.
One or more RAM sections can be retained in System OFF depending on the RAM retention settings configured in MEMCONF — Memory configuration.
- All on-going EasyDMA transactions must finish. See peripheral specific chapters for more information about how to get the status of EasyDMA transactions.
- The 32 MHz oscillator (HFXO) must be stopped. Stop HFXO with the XOSTOP task. The 32 kHz oscillator (LFXO) can be running.
- The register RESET.RESETREAS must be cleared. Failure to do so can make the system immediately wake up from System OFF mode.
Emulated System OFF mode
When the device is in Debug Interface mode, System OFF is emulated to ensure that all resources required for debugging are available during System OFF.
Resources required for debugging include the following key components:
- Debug Interface mode
- CLOCK — Clock control
- POWER — Power control
- OSCILLATORS — Oscillator control
- REGULATORS — Regulator control
- RESET — Reset control
- CPU
- Memory
Because the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop directly after entering System OFF. This prevents the CPU from executing code that normally should not be executed. For more information, see Debug and trace.