REGULATORS — Regulator control

The power supply consists of a main regulator VREGMAIN that maximize the system's power efficiency.

All system components are powered from the main on-chip voltage regulator, VREGMAIN. The regulator converts the voltage supplied on VDD to internal voltage.

VREGMAIN — Main regulator

VREGMAIN is the main regulator of the system.

The device only supports DC/DC mode, which needs external components. For details, see Reference circuitry.

VREGMAIN starts up using a fall-back mode, and the DC/DC regulator must be enabled using register VREGMAIN.DCDCEN.

Inductor detection

The DC/DC regulator requires an external inductor connected to the DCC pin. If an inductor is not present, the regulator stays in fall-back mode to enable a soft shut-down of the system. Register VREGMAIN.INDUCTORDET reports the inductor detection status and can be used to detect inductor failures that prevent DC/DC operation.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
REGULATORS : S REGULATORS : NS	GLOBAL	0x50120000 0x40120000	US	S	NA	No	Regulator control

Register overview


Register	Offset	Description
HIBERNATOR.SYSTEMHIBERNATE	0x400	Enter System hibernation mode for extreme low power consumption
HIBERNATOR.GPIORETENTIONRELEASE	0x404	Release GPIO retention on wake up from hibernation mode.
HIBERNATOR.GPIORETENTIONSTATUS	0x408	Read out if GPIO retention is active.
SYSTEMOFF	0x500	System OFF register
POFCON	0x530	Power-fail comparator configuration This register is retained.
POFSTAT	0x534	Power-fail comparator status register
VREGMAIN.DCDCEN	0x600	Enable DC/DC converter
VREGMAIN.INDUCTORDET	0x604	VREGMAIN inductor detection

HIBERNATOR

Hibernator interface

HIBERNATOR.SYSTEMHIBERNATE

Address offset: 0x400

Enter System hibernation mode for extreme low power consumption


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	SYSTEMHIBERNATE										Enter hibernation mode
			Enter	1								Enter hibernation mode

HIBERNATOR.GPIORETENTIONRELEASE

Address offset: 0x404

Release GPIO retention on wake up from hibernation mode.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	GPIORETENTIONRELEASE										Release GPIO retention
			NoRelease	0								Do not release retention
			Release	1								Release retention

HIBERNATOR.GPIORETENTIONSTATUS

Address offset: 0x408

Read out if GPIO retention is active.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	GPIORETENTIONSTATUS										Read out if GPIO retention is active.
			NotActive	0								GPIO retention is not active.
			Active	1								GPIO retention is active.

SYSTEMOFF

Address offset: 0x500

System OFF register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	SYSTEMOFF										Enable System OFF mode
			Enter	1								Enable System OFF mode

POFCON (Retained)

Address offset: 0x530

Power-fail comparator configuration

This register is retained.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			D									C			B	B	B	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	POF										Enable or disable power-fail comparator
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	THRESHOLD										Power-fail comparator threshold setting
			V090	0								Set threshold to 0.90 V for VDDL
			V095	1								Set threshold to 0.95 V for VDDL
			V100	2								Set threshold to 1.00 V for VDDL
			V105	3								Set threshold to 1.05 V for VDDL
			V110	4								Set threshold to 1.10 V for VDDL
			V115	5								Set threshold to 1.15 V for VDDL
			V120	6								Set threshold to 1.20 V for VDDL
			V125	7								Set threshold to 1.25 V for VDDL
			V130	8								Set threshold to 1.30 V for VDDL
			V135	9								Set threshold to 1.35 V for VDDL
			V140	10								Set threshold to 1.40 V for VDDL
			V145	11								Set threshold to 1.45 V for VDDL
			V150	12								Set threshold to 1.50 V for VDDL
			V155	13								Set threshold to 1.55 V for VDDL
			V160	14								Set threshold to 1.60 V for VDDL
			V165	15								Set threshold to 1.65 V for VDDL
C	RW	EVENTDISABLE										Disable the POFWARN power-fail warning event
			Enabled	0								POFWARN event is generated
			Disabled	1								POFWARN event is not generated
D	RW	PSEL										Power-fail comparator input selector
			VddL	1								POF input connected to VDDL

POFSTAT

Address offset: 0x534

Power-fail comparator status register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	COMPARATOR										Power-fail comparator status
			Above	0								Voltage detected above VPOF threshold
			Below	1								Voltage detected below VPOF threshold

VREGMAIN

VREGMAIN.DCDCEN

Address offset: 0x600

Enable DC/DC converter


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	VAL										Enable DC/DC buck converter
			Disabled	0								Disable DC/DC buck converter
			Enabled	1								Enable DC/DC converter If inductor is not present (see register VREGMAIN.INDUCTORDET), the DC/DC converter cannot operate

VREGMAIN.INDUCTORDET

Address offset: 0x604

VREGMAIN inductor detection

Ensure that an inductor is connected to the DCC pin. The detection can only take place before the DC/DC converter is enabled.

Note: The DC/DC converter cannot operate without an inductor.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DETECTED
			InductorNotDetected	0								VREGMAIN inductor not detected
			InductorDetected	1								VREGMAIN inductor detected