TIMER — Timer/counter

The TIMER peripheral is a general purpose timer allowing time intervals to be defined by user input.

The main features of TIMER are:

Two modes of operation: Timer mode and Counter mode
Multiple capture/compare registers
Compare event for every capture/compare registers
4-bit (1/2X) prescaler
Configurable number of bits used by the TIMER: 8, 16, 24 or 32 bits
TIMER runs on the high-frequency clock source (HFCLK)

Figure 1. Block schematic for timer/counter

TIMER runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X) prescaler that can divide the timer input clock (PCLK) from the HFCLK controller. The TIMER base frequency is always given as PCLK divided by the prescaler value.

The PPI system allows a TIMER event to trigger a task on another system peripheral on the device. The PPI system also enables the TIMER task/event feature to generate periodic output and PWM signals to any GPIO. The number of GPIO inputs or outputs used at the same time is limited by the number of GPIOTE channels.

TIMER can operate in two modes: Timer mode and Counter mode. In both modes, TIMER is started by triggering the START task, and stopped by triggering the STOP task. After TIMER stops, it can resume timing/counting by triggering the START task again. When timing/counting resumes, TIMER continues from the value it was on prior to stopping.

In Timer mode, TIMER's internal Counter register is incremented by one for every tick of the timer frequency f_TIMER, as illustrated in Block schematic for timer/counter. The timer frequency is derived from PCLK as shown in the following example, using the values specified in the PRESCALER register.


    f_TIMER = PCLK / (2^PRESCALER)

For timers using PCLK16M as PCLK, when f_TIMER ≤ 1 MHz, TIMER uses PCLK1M instead of PCLK for reduced power consumption. Clock source selection between PCLK and PCLK1M is automatic according to the TIMER base frequency set by the prescaler.

In Counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task is triggered, meaning the timer frequency and the prescaler are not utilized in Counter mode. Similarly, the COUNT task has no effect in Timer mode.

TIMER's maximum value is configured by changing the bit-width of the timer in register BITMODE.

PRESCALER and BITMODE must only be updated when TIMER is stopped. If these registers are updated while TIMER is started, unpredictable behavior may occur.

When TIMER is incremented beyond its maximum value, the Counter register will overflow and TIMER will automatically start over from zero.

The Counter register can be cleared by triggering the CLEAR task. This will explicitly set the internal value to zero.

TIMER implements multiple capture/compare registers.

Independent of prescaler settings, the accuracy of TIMER is equivalent to one tick of the timer frequency f_TIMER as illustrated in Block schematic for timer/counter.

Capture

TIMER implements one capture task for every available capture/compare register.

Every time the CAPTURE[n] task is triggered, the counter value is copied to the CC[n] register.

Compare

TIMER implements one COMPARE event for every available capture/compare register.

When the counter value becomes equal to the value specified in a capture compare register CC[n], the corresponding compare event COMPARE[n] is generated.

BITMODE specifies how many Counter and capture/compare register bits are used when the comparison is performed. Other bits are ignored.

The COMPARE event can be configured to operate in one-shot mode by configuring the corresponding ONESHOTEN[n] register. After writing CC[n], a COMPARE[n] event is generated the first time the Counter matches CC[n].

Task delays

After TIMER is started, the CLEAR, COUNT, and STOP tasks are guaranteed to take effect within one clock cycle of the PCLK.

Task priority

If the START task and the STOP task are triggered at the same time, meaning within the same period of PCLK, the STOP task is prioritized.

If one or more of the CAPTURE tasks and the CLEAR task are triggered at the same time, that is, within the same period of PCLK, the CAPTURE tasks are prioritized. This means that the CC registers will capture the counter value before the CLEAR tasks are triggered.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
TIMER00 : S TIMER00 : NS	GLOBAL	0x50055000 0x40055000	US	S	NA	No	Timer TIMER00
TIMER10 : S TIMER10 : NS	GLOBAL	0x50085000 0x40085000	US	S	NA	No	Timer TIMER10
TIMER20 : S TIMER20 : NS	GLOBAL	0x500CA000 0x400CA000	US	S	NA	No	Timer TIMER20
TIMER21 : S TIMER21 : NS	GLOBAL	0x500CB000 0x400CB000	US	S	NA	No	Timer TIMER21
TIMER22 : S TIMER22 : NS	GLOBAL	0x500CC000 0x400CC000	US	S	NA	No	Timer TIMER22
TIMER23 : S TIMER23 : NS	GLOBAL	0x500CD000 0x400CD000	US	S	NA	No	Timer TIMER23
TIMER24 : S TIMER24 : NS	GLOBAL	0x500CE000 0x400CE000	US	S	NA	No	Timer TIMER24

Configuration


Instance	Domain	Configuration
TIMER00 : S TIMER00 : NS	GLOBAL	Peripheral clock frequency (PCLK) is 128 MHz The system is able to configure the TIMER peripheral input clock frequency (PCLK) before it reaches TIMER, and calculations of PRESCALER value must take the actual PCLK frequency into account 6 capture compare channels implemented
TIMER10 : S TIMER10 : NS	GLOBAL	Peripheral clock frequency (PCLK) is 32 MHz 8 capture compare channels implemented
TIMER20 : S TIMER20 : NS	GLOBAL	Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented
TIMER21 : S TIMER21 : NS	GLOBAL	Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented
TIMER22 : S TIMER22 : NS	GLOBAL	Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented
TIMER23 : S TIMER23 : NS	GLOBAL	Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented
TIMER24 : S TIMER24 : NS	GLOBAL	Peripheral clock frequency (PCLK) is 16 MHz 6 capture compare channels implemented

Register overview


Register	Offset	Description
TASKS_START	0x000	Start Timer
TASKS_STOP	0x004	Stop Timer
TASKS_COUNT	0x008	Increment Timer (Counter mode only)
TASKS_CLEAR	0x00C	Clear time
TASKS_CAPTURE[n]	0x040	Capture Timer value to CC[n] register
SUBSCRIBE_START	0x080	Subscribe configuration for task START
SUBSCRIBE_STOP	0x084	Subscribe configuration for task STOP
SUBSCRIBE_COUNT	0x088	Subscribe configuration for task COUNT
SUBSCRIBE_CLEAR	0x08C	Subscribe configuration for task CLEAR
SUBSCRIBE_CAPTURE[n]	0x0C0	Subscribe configuration for task CAPTURE[n]
EVENTS_COMPARE[n]	0x140	Compare event on CC[n] match
PUBLISH_COMPARE[n]	0x1C0	Publish configuration for event COMPARE[n]
SHORTS	0x200	Shortcuts between local events and tasks
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
MODE	0x504	Timer mode selection
BITMODE	0x508	Configure the number of bits used by the TIMER
PRESCALER	0x510	Timer prescaler register
CC[n]	0x540	Capture/Compare register n
ONESHOTEN[n]	0x580	Enable one-shot operation for Capture/Compare channel n

TASKS_START

Address offset: 0x000

Start Timer


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_START										Start Timer
			Trigger	1								Trigger task

TASKS_STOP

Address offset: 0x004

Stop Timer


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_STOP										Stop Timer
			Trigger	1								Trigger task

TASKS_COUNT

Address offset: 0x008

Increment Timer (Counter mode only)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_COUNT										Increment Timer (Counter mode only)
			Trigger	1								Trigger task

TASKS_CLEAR

Address offset: 0x00C

Clear time


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_CLEAR										Clear time
			Trigger	1								Trigger task

TASKS_CAPTURE[n]

Address offset: 0x040 + (n × 0x4)

Capture Timer value to CC[n] register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_CAPTURE										Capture Timer value to CC[n] register
			Trigger	1								Trigger task

Address offset: 0x080

Subscribe configuration for task START


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task START will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

Address offset: 0x084

Subscribe configuration for task STOP


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task STOP will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

Address offset: 0x088

Subscribe configuration for task COUNT


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task COUNT will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

Address offset: 0x08C

Subscribe configuration for task CLEAR


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task CLEAR will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

Address offset: 0x0C0 + (n × 0x4)

Subscribe configuration for task CAPTURE[n]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task CAPTURE[n] will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

EVENTS_COMPARE[n]

Address offset: 0x140 + (n × 0x4)

Compare event on CC[n] match


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_COMPARE										Compare event on CC[n] match
			NotGenerated	0								Event not generated
			Generated	1								Event generated

PUBLISH_COMPARE[n]

Address offset: 0x1C0 + (n × 0x4)

Publish configuration for event COMPARE[n]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event COMPARE[n] will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												P	O	N	M	L	K	J	I									H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-H	RW	COMPARE[i]_CLEAR (i=0..7)										Shortcut between event COMPARE[i] and task CLEAR
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
I-P	RW	COMPARE[i]_STOP (i=0..7)										Shortcut between event COMPARE[i] and task STOP
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-H	RW	COMPARE[i] (i=0..7)										Enable or disable interrupt for event COMPARE[i]
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-H	RW W1S	COMPARE[i] (i=0..7)										Write '1' to enable interrupt for event COMPARE[i]
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-H	RW W1C	COMPARE[i] (i=0..7)										Write '1' to disable interrupt for event COMPARE[i]
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

MODE

Address offset: 0x504

Timer mode selection


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MODE										Timer mode
			Timer	0								Select Timer mode
			Counter	1								Select Counter mode This enumerator is deprecated.
			LowPowerCounter	2								Select Low Power Counter mode

BITMODE

Address offset: 0x508

Configure the number of bits used by the TIMER


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	BITMODE										Timer bit width
			16Bit	0								16 bit timer bit width
			08Bit	1								8 bit timer bit width
			24Bit	2								24 bit timer bit width
			32Bit	3								32 bit timer bit width

PRESCALER

Address offset: 0x510

Timer prescaler register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																A	A	A	A
Reset 0x00000004				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PRESCALER		[0..9]								Prescaler value

CC[n]

Address offset: 0x540 + (n × 0x4)

Capture/Compare register n


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CC										Capture/Compare value Only the number of bits indicated by BITMODE will be used by the TIMER.

ONESHOTEN[n]

Address offset: 0x580 + (n × 0x4)

Enable one-shot operation for Capture/Compare channel n


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ONESHOTEN										Enable one-shot operation Configures the corresponding compare-channel for one-shot operation
			Disable	0								Disable one-shot operation Compare event is generated every time the Counter matches CC[n]
			Enable	1								Enable one-shot operation Compare event is generated the first time the Counter matches CC[n] after CC[n] has been written