UARTE — Universal asynchronous receiver/transmitter with EasyDMA

The UART baudrate defines the speed at which data is transmitted over the UART interface, measured in bits per second (bps).

The BAUDRATE register lists a set of precalculated values for the most common baudrates and 16 MHz PCLK. For the high speed instances (PCLK > 16 MHz), the baudrate is calculated as follows:

• BAUDRATE is the value to be used in the UARTE BAUDRATE register.
• f_PCLK is the peripheral clock frequency for the UARTE instance, as defined in Instances.
• desired_baudrate is the desired baudrate in bits per second, such as 9600 or 115200.

UARTE implements EasyDMA for reading and writing to and from RAM.

If the DMA.TX.PTR and the DMA.RX.PTR are not pointing to the RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about each memory region.

The DMA.RX.PTR, DMA.TX.PTR, DMA.RX.MAXCNT, and DMA.TX.MAXCNT registers are double-buffered. They can be updated and prepared for the next reception or transmission immediately after having received the DMA.RX.READY or DMA.TX.READY events.

The DMA.RX.END and DMA.TX.END events indicate that the EasyDMA is finished accessing the RX or TX buffer in RAM.

For detailed information regarding the use of EasyDMA, see EasyDMA.

The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This is achieved by writing the initial address pointer to DMA.TX.PTR, and the number of bytes to transmit from the RAM buffer to DMA.TX.MAXCNT. The UARTE transmission is started by triggering the DMA.TX.START task.

After each byte has been sent over the TXD line, a TXDRDY event is generated.

When then bytes have been transmitted, the DMA.TX.END event is generated.

A UARTE transmission sequence is stopped by triggering the DMA.TX.STOP task. A TXSTOPPED event will be generated when the UARTE transmitter has stopped.

If the DMA.TX.END event has not been generated when the UARTE transmitter stops, UARTE will generate the DMA.TX.END event explicitly even though all bytes specified in the DMA.TX.MAXCNT register have not been transmitted.

If flow control is enabled in the HWFC field in the CONFIG register, a transmission will be automatically suspended when CTS is deactivated, and resumed when CTS is activated again, as shown in the following figure. A byte that is in transmission when CTS is deactivated will finish transmitting before the transmission is suspended.

The UARTE transmitter is least active when it is stopped, consuming the least amount of energy. This is before it is started via DMA.TX.START, or after it has been stopped via DMA.TX.STOP and the TXSTOPPED event has been generated. See POWER — Power control for more information about power modes.

The UARTE receiver is started by triggering the DMA.RX.START task. The UARTE receiver uses EasyDMA to store incoming data in an RX buffer in RAM.

The RX buffer is located at the address specified in the DMA.RX.PTR register. The DMA.RX.PTR register is double-buffered and can be updated and prepared for the next DMA.RX.START task immediately after the EVENTS_DMA.RX.READY event is generated. The size of the RX buffer is specified in the DMA.RX.MAXCNT register. UARTE generates an DMA.RX.END event when it has filled up the RX buffer, as seen in the following figure.

For each byte received over the RXD line, an RXDRDY event is generated. This event is likely to occur before the corresponding data has been transferred to RAM.

The DMA.RX.AMOUNT register can be queried following an DMA.RX.END event to see how many new bytes have been transferred to the RX buffer in RAM since the previous DMA.RX.END event.

The UARTE receiver is stopped by triggering the DMA.RX.STOP task. The RXTO and DMA.RX.END events are generated when UARTE has stopped.

Stopping the UARTE with a RX buffer that is empty or not completely filled up will also cause the DMA.RX.END event to be generated.

The number of bytes stored in the RX buffer can be found by reading the DMA.RX.AMOUNT register following the DMA.RX.END event.

To stop UARTE, trigger the DMA.RX.STOP task. After the STOP task is triggered, UARTE can receive up to four bytes during the timeout period. The data received during the timeout period will be written to DMA.RX.PTR, and limited by DMA.RX.MAXCNT registers. MAXCNT should be set to at least four bytes to allow for this, while following the DMA.RX.END event, the DMA.RX.AMOUNT register will indicate the actual number of bytes received.

If hardware flow control is enabled in the HWFC field in the CONFIG register, the RTS signal will be deactivated when the receiver is stopped via the DMA.RX.STOP task, or when UARTE can only receive three more bytes in its internal RX FIFO.

With flow control disabled, the UARTE will function in the same way as when the flow control is enabled, except that the RTS line will not be used. This means that no signal will be generated when UARTE is only able to receive three additional bytes in its internal RX FIFO. Data received when the internal RX FIFO is full, will be lost.

The UARTE receiver is least active when it is stopped, consuming the least amount of energy. This is before it is started via DMA.RX.START, or after it has been stopped via DMA.RX.STOP and the RXTO event has been generated. See POWER — Power control for more information about power modes.

UARTE implements a configurable data frame size of 4 bits to 9 bits and is set in the register CONFIG. If a value greater than 9 or less than 4 is written to this register, the frame size will be set to 8 bits and the register will read back a value of 8.

When UARTE is used with the 9 bit frame size, a 9th bit is added after the MSB of the 8 bit data frame, and before the parity and stop bits, as shown in the following figure. This bit indicates if the 8 bit data is an address or data. If the 9th bit is 1, the 8 bit data is interpreted as an address. If the 9th bit is 0, the 8 bit data is interpreted as data.

When UART is in RX configured with a 9 bit frame size, all frames are ignored until a frame with the address bit set is received, and the 8 remaining bits of the data frame matches the address set in the register ADDRESS. The frames following the matching address are received as an 8 bit data frame until the next frame where the address bit set is received, the address bit is not stored. If the address does not match ADDRESS, the following frames are ignored.

If the parity bit is enabled, the address bit is not included in the parity calculation.

When UART TX is started, the first byte in the buffer read by EasyDMA is treated as an address, and transmitted with the address bit set to 1. The next bits in the buffer are treated as data and transmitted with the address bit set to 0.

When UARTE uses a data frame size less than an 8 bits, the data is trimmed from an 8 bit frame size in the RAM buffer for TX, and padded before being stored in the RAM buffer for RX. The ENDIAN field in the register CONFIG defines if the data is trimmed from MSB or LSB of the 8 bit buffer frame.

UARTE can generate an event after a programmable timeout.

If enabled with the FRAMETIMEOUT field in register CONFIG, a counter starts at the start flag, and counts the number of bit periods given in register FRAMETIMEOUT. The period time of the counter is equal to the period of one bit on the UART TX line given by the BAUDRATE register. When the timeout expires, the event EVENTS_FRAMETIMEOUT is generated. The STOP task also stops the timeout counter. UARTE reception can be stopped on timeout by setting the short from the FRAMETIMEOUT event to the DMA.RX.STOP task in register SHORTS.

This feature can be used to support variable length UART transmission with no end of transmission tag. After the last UART frames are received within the configured timeout, an interrupt is generated and the data can be processed.

The following figure shows an example where the UART receives a transmission that times out after byte 12.

The minimum value of the FRAMETIMEOUT register must be set to a value larger than the configured UART frame length.

An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. A framing error is always generated before a break condition occurs.

An ERROR event will not stop reception. If the error was a parity error, the received byte is still transferred into RAM along with any following bytes. If a framing error occurs (wrong stop bit), that byte will not be stored in RAM but the next incoming bytes will.

Automatic even parity generation for both transmission and reception can be configured using the register CONFIG. If odd parity is required, it can be configured using the register CONFIG. See the register description for details.

The amount of stop bits can be configured in the register CONFIG.

UARTE has a compare match filter that can watch for a specific sequence of data. This feature is implemented in EasyDMA on the RX channel.

UARTE can generate events or interrupts when the specific data sequence is received. The event EVENTS_DMA.RX.MATCH[n] (n=0..3) is generated when there is a match in the data stream being received. The number of MATCH can be different for each instance. See Registers for how many MATCH events are implemented per instance.

Register DMA.RX.MATCH.CANDIDATE[n] (n=0..3) configures the pattern for comparison. The filter is enabled with the corresponding ENABLE bit in register DMA.RX.MATCH.CONFIG. The DMA.RX.ENABLEMATCH task can be used to set that bit, and the DMA.RX.DISABLEMATCH task will clear that bit. If the ONESHOT[i] field in the CONFIG register is set, the corresponding ENABLE[i] bit will be cleared on a successful match.

For detailed information regarding the use of pattern matching in the EasyDMA engine, see EasyDMA.

To ensure lowest possible power consumption when the peripheral is not needed, stop and disable UARTE.

The DMA.TX.STOP and DMA.RX.STOP tasks are not always needed (the peripheral might already be stopped). If DMA.TX.STOP or DMA.RX.STOP is sent, software waits until the TXSTOPPED or RXTO event is received before disabling the peripheral through the ENABLE register.

The RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD signals associated with UARTE are mapped to physical pins according to the configuration specified in the PSEL.n registers.

These registers and their configurations are only used when UARTE is enabled, and retained while the device is in System ON mode. The PSEL.n registers can be configured only when UARTE is disabled.

To ensure correct behavior when in System OFF mode, the pins must be configured in the GPIO peripheral as described in the following table.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.