SPIS Electrical specification

SPIS slave interface electrical specifications


Symbol	Description	Min.	Typ.	Max.	Units
f_SPIS	Bit rates for SPIS²			8³	Mbps
t_SPIS,START	Time from RELEASE task to receive/transmit (CSN active)		1		µs

² High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.

³ The actual maximum data rate depends on the master's CLK to SDO and SDI setup and hold timings.


Symbol	Description	Min.	Max.	Units
t_SPIS,CSCKIN	SCK input period	125		ns
t_SPIS,RFSCKIN	SCK input rise/fall time		30	ns
t_SPIS,WHSCKIN	SCK input high time	30		ns
t_SPIS,WLSCKIN	SCK input low time	30		ns
t_SPIS,SUCSN	CSN to CLK setup time	1000⁴		ns
t_SPIS,HCSN	CLK to CSN hold time	1000		ns
t_SPIS,ASA	CSN to SDO driven		70	ns
t_SPIS,ASO	CSN to SDO valid^⁵		1000	ns
t_SPIS,DISSO	CSN to SDO disabled^⁵		70	ns
t_SPIS,CWH	CSN inactive time	300		ns

⁴ Excluding any start-up delay for the high frequency clock in low power mode.

⁵ At 25pF load, including GPIO capacitance, see GPIO spec.


Symbol	Description	Min.	Max.	Units
t_SPIS,VSO	CLK edge to SDO valid		89	ns
t_SPIS,HSO	SDO hold time after CLK edge	7		ns
t_SPIS,SUSI	SDI to CLK edge setup time	16		ns
t_SPIS,HSI	CLK edge to SDI hold time	1		ns


Symbol	Description	Min.	Max.	Units
t_SPIS,VSO	CLK edge to SDO valid		69	ns
t_SPIS,HSO	SDO hold time after CLK edge	6		ns
t_SPIS,SUSI	SDI to CLK edge setup time	16		ns
t_SPIS,HSI	CLK edge to SDI hold time	1		ns


Symbol	Description	Min.	Max.	Units
t_SPIS,VSO	CLK edge to SDO valid		83	ns
t_SPIS,HSO	SDO hold time after CLK edge	6		ns
t_SPIS,SUSI	SDI to CLK edge setup time	4		ns
t_SPIS,HSI	CLK edge to SDI hold time	3		ns


Symbol	Description	Min.	Max.	Units
t_SPIS,VSO	CLK edge to SDO valid		61	ns
t_SPIS,HSO	SDO hold time after CLK edge	6		ns
t_SPIS,SUSI	SDI to CLK edge setup time	4		ns
t_SPIS,HSI	CLK edge to SDI hold time	3		ns