SWDP Electrical specification

SW-DP

SymbolDescriptionMin.Typ.Max.Units
Rpull

Internal SWDIO and SWDCLK pull up/down resistance

14kΩ
fSWDCLK

SWDCLK frequency

0.12520MHz
tSUI

SWDIO input setup before SWDCLK

18ns
tHI

SWDIO input hold after SWDCLK

2ns
tVO

SWDCLK to SWDIO output valid

67ns
tHO

SWDIO output hold after SWDCLK

7ns
Figure 5. SWD timing diagram
SWD timing diagram

Trace port

SymbolDescriptionMin.Typ.Max.Units
Tcyc

Clock period, as defined by Arm in Embedded Trace Macrocell Architecture Specification

15.625250ns